公开(公告)号：US20140285980A1

公开(公告)日：2014-09-25

申请号：US13976068

申请日：2012-04-13

申请人： Annalisa Cappellani ,  Van H. Le ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Stephen M. Cea

发明人： Annalisa Cappellani ,  Van H. Le ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Stephen M. Cea

IPC分类号： H01L29/06 ,  H01L21/02 ,  H05K1/18

CPC分类号： H01L29/66795 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/76 ,  H01L21/7624 ,  H01L21/76283 ,  H01L29/0603 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/7378 ,  H01L29/785 ,  H01L33/12 ,  H05K1/18

摘要： Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.

摘要翻译： 公开了用于将应变诱导半导体缓冲层转化为缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括由于生长而产生的那些 在应变诱导缓冲器上并具有埋入的电绝缘体层。 例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fin 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。 此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。 在一些实施例中，基本上整个缓冲层被转换成电绝缘体。

公开(公告)号：US09129827B2

公开(公告)日：2015-09-08

申请号：US13976068

申请日：2012-04-13

申请人： Annalisa Cappellani ,  Van H. Le ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Stephen M. Cea

发明人： Annalisa Cappellani ,  Van H. Le ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Stephen M. Cea

IPC分类号： H01L33/12 ,  H01L29/06 ,  H01L21/76 ,  H01L21/02 ,  H05K1/18 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/66795 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/76 ,  H01L21/7624 ,  H01L21/76283 ,  H01L29/0603 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/7378 ,  H01L29/785 ,  H01L33/12 ,  H05K1/18

摘要： Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.

摘要翻译： 公开了用于将应变诱导半导体缓冲层转化为缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括由于生长而产生的那些 在应变诱导缓冲器上并具有埋入的电绝缘体层。 例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fe 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。 此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。 在一些实施例中，基本上整个缓冲层被转换成电绝缘体。

公开(公告)号：US09583491B2

公开(公告)日：2017-02-28

申请号：US14948083

申请日：2015-11-20

申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10

CPC分类号： H01L21/823821 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

摘要翻译： 描述了免费的金属氧化物半导体纳米线结构。 例如，半导体结构包括第一半导体器件。 第一半导体器件包括设置在衬底之上的第一纳米线。 第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一栅极电极堆叠完全包围第一纳米线的离散通道区域。 半导体结构还包括第二半导体器件。 第二半导体器件包括设置在衬底上方的第二纳米线。 第二纳米线在衬底上方具有第二距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一距离与第二距离不同。 第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

公开(公告)号：US20160086951A1

公开(公告)日：2016-03-24

申请号：US14948083

申请日：2015-11-20

申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L21/823821 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

摘要翻译： 描述了免费的金属氧化物半导体纳米线结构。 例如，半导体结构包括第一半导体器件。 第一半导体器件包括设置在衬底之上的第一纳米线。 第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一栅极电极堆叠完全包围第一纳米线的离散通道区域。 半导体结构还包括第二半导体器件。 第二半导体器件包括设置在衬底上方的第二纳米线。 第二纳米线在衬底上方具有第二距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一距离与第二距离不同。 第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

公开(公告)号：US09224810B2

公开(公告)日：2015-12-29

申请号：US13996503

申请日：2011-12-23

申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L21/823821 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

摘要翻译： 描述了免费的金属氧化物半导体纳米线结构。 例如，半导体结构包括第一半导体器件。 第一半导体器件包括设置在衬底之上的第一纳米线。 第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一栅极电极堆叠完全包围第一纳米线的离散通道区域。 半导体结构还包括第二半导体器件。 第二半导体器件包括设置在衬底上方的第二纳米线。 第二纳米线在衬底上方具有第二距离的中点，并且在离散通道区域的任一侧上包括离散通道区域和源极和漏极区域。 第一距离与第二距离不同。 第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

公开(公告)号：US20140197377A1

公开(公告)日：2014-07-17

申请号：US13996503

申请日：2011-12-23

申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

IPC分类号： H01L29/06 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823821 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

摘要翻译： 描述了免费的金属氧化物半导体纳米线结构。 例如，半导体结构包括第一半导体器件。 第一半导体器件包括设置在衬底之上的第一纳米线。 第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一栅极电极堆叠完全包围第一纳米线的离散通道区域。 半导体结构还包括第二半导体器件。 第二半导体器件包括设置在衬底上方的第二纳米线。 第二纳米线在衬底上方具有第二距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一距离与第二距离不同。 第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

公开(公告)号：US09559160B2

公开(公告)日：2017-01-31

申请号：US13996506

申请日：2011-12-23

申请人： Annalisa Cappellani ,  Peter G. Tolchinsky ,  Kelin J. Kuhn ,  Glenn A. Glass ,  Van H. Le

发明人： Annalisa Cappellani ,  Peter G. Tolchinsky ,  Kelin J. Kuhn ,  Glenn A. Glass ,  Van H. Le

IPC分类号： H01L29/04 ,  H01L29/66 ,  H01L29/775 ,  H01L27/12 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/045 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78687 ,  H01L29/78696

摘要： Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.

摘要翻译： 描述具有不同材料取向或组成的纳米线或半导体主体的共基板半导体器件以及形成这种共基板器件的方法。 例如，半导体结构包括具有设置在结晶衬底之上的第一纳米线或半导体本体的第一半导体器件。 第一纳米线或半导体主体由具有第一全局晶体取向的半导体材料组成。 半导体结构还包括具有设置在晶体衬底上方的第二纳米线或半导体本体的第二半导体器件。 第二纳米线或半导体本体由具有与第一全局取向不同的第二全局晶体取向的半导体材料组成。 通过设置在第二纳米线或半导体本体与晶体衬底之间的隔离基座，将第二纳米线或半导体本体与晶体衬底隔离。

公开(公告)号：US20130320294A1

公开(公告)日：2013-12-05

申请号：US13996506

申请日：2011-12-23

申请人： Annalisa Cappellani ,  Peter G. Tolchinsky ,  Kelin J. Kuhn ,  Glenn A. Glass ,  Van H. Le

发明人： Annalisa Cappellani ,  Peter G. Tolchinsky ,  Kelin J. Kuhn ,  Glenn A. Glass ,  Van H. Le

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78687 ,  H01L29/78696

摘要： Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.

摘要翻译： 描述具有不同材料取向或组成的纳米线或半导体主体的共基板半导体器件以及形成这种共基板器件的方法。 例如，半导体结构包括具有设置在结晶衬底之上的第一纳米线或半导体本体的第一半导体器件。 第一纳米线或半导体主体由具有第一全局晶体取向的半导体材料组成。 半导体结构还包括具有设置在晶体衬底上方的第二纳米线或半导体本体的第二半导体器件。 第二纳米线或半导体本体由具有与第一全局取向不同的第二全局晶体取向的半导体材料组成。 通过设置在第二纳米线或半导体本体与晶体衬底之间的隔离基座将第二纳米线或半导体本体与晶体衬底隔离。

公开(公告)号：US08753942B2

公开(公告)日：2014-06-17

申请号：US12958179

申请日：2010-12-01

申请人： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

发明人： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

IPC分类号： H01L29/775 ,  H01L29/66 ,  H01L21/336 ,  H01L21/762 ,  H01L29/772 ,  B82Y40/00

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间​​的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

公开(公告)号：US20120138886A1

公开(公告)日：2012-06-07

申请号：US12958179

申请日：2010-12-01

申请人： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

发明人： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

IPC分类号： H01L29/775 ,  H01L29/66 ,  H01L21/336 ,  H01L21/762 ,  B82Y40/00 ,  H01L29/772

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间​​的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。