公开(公告)号：US20150221730A1

公开(公告)日：2015-08-06

申请号：US14688512

申请日：2015-04-16

Applicant: APPLIED MATERIALS, INC.

Inventor： Zhiyuan YE ,  Xuebin LI ,  Saurabh CHOPRA ,  Yihwan KIM

IPC: H01L29/36 ,  H01L29/167

CPC classification number: H01L29/36 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02664 ,  H01L21/823814 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device. The devices include epitaxial layers having a resistivity of less than about 0.381 milliohm-centimeters.

Abstract translation: 本发明的实施例一般涉及形成外延层的方法和具有外延层的器件。 所述方法通常包括在衬底上形成包括磷和碳的第一外延层，然后在第一外延层上形成包括磷和碳的第二外延层。 第二外延层具有比第一外延层更低的磷浓度，其允许在沉积期间沉积的第二外延层和不期望的非晶硅或多晶硅的选择性蚀刻。 然后将衬底暴露于蚀刻剂以除去第二外延层和不期望的非晶硅或多晶硅。 存在于第一和第二外延层中的碳减少磷扩散，这允许更高的磷掺杂浓度。 增加的磷浓度降低了最终装置的电阻率。 这些器件包括具有小于约0.381毫欧姆厘米的电阻率的外延层。

公开(公告)号：US20150368796A1

公开(公告)日：2015-12-24

申请号：US14744296

申请日：2015-06-19

Applicant: Applied Materials, Inc.

Inventor： Xuebin LI ,  Kevin JOSEPH BAUTISTA ,  Avinash SHERVEGAR ,  Yihwan KIM ,  Nyi O. MYO ,  Abhishek DUBE

IPC: C23C16/455 ,  F16L41/02

CPC classification number: C23C16/45504 ,  C23C16/24 ,  C23C16/4412 ,  C23C16/4551 ,  C23C16/45563 ,  C30B25/14 ,  C30B35/00

Abstract: Embodiments described herein generally relate to apparatus for forming silicon epitaxial layers on semiconductor devices. Deposition gases and etching gases may be provided sequentially or simultaneously to improve epitaxial layer deposition characteristics. A gas distribution assembly may be coupled to a deposition gas source and an etching gas source. Deposition gas and etching gas may remain separated until the gases are provided to a processing volume in a processing chamber. Outlets of the gas distribution assembly may be configured to provide the deposition gas and etching gas into the processing volume with varying characteristics. In one embodiment, outlets of the gas distribution assembly which deliver etching gas to the processing volume may be angled upward relative to a surface of a substrate.

Abstract translation: 本文描述的实施例一般涉及用于在半导体器件上形成硅外延层的装置。 可以顺序地或同时地提供沉积气体和蚀刻气体以改善外延层沉积特性。 气体分配组件可以耦合到沉积气体源和蚀刻气体源。 沉积气体和蚀刻气体可以保持分离，直到气体被提供到处理室中的处理体积。 气体分配组件的出口可以被配置成将沉积气体和蚀刻气体提供到具有不同特征的处理体积中。 在一个实施例中，将蚀刻气体输送到处理容积的气体分配组件的出口可以相对于衬底的表面向上倾斜。

公开(公告)号：US20170098547A1

公开(公告)日：2017-04-06

申请号：US15384051

申请日：2016-12-19

Applicant: Applied Materials, Inc.

Inventor： Yihwan KIM ,  Xuebin LI ,  Abhishek DUBE

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/3083 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02639 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/66795

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. An epitaxial film is formed over a semiconductor fin, and the epitaxial film includes a top surface having two facets. A cap layer is deposited on the top surface, and portions of the epitaxial film in a lateral direction are removed. Having a smaller lateral dimension prevents the epitaxial film from merging with an adjacent epitaxial film and creates a gap between the epitaxial film and the adjacent epitaxial film.

公开(公告)号：US20160042963A1

公开(公告)日：2016-02-11

申请号：US14799387

申请日：2015-07-14

Applicant: APPLIED MATERIALS, INC.

Inventor： Yihwan KIM ,  Xuebin LI ,  Abhishek DUBE

IPC: H01L21/308 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/3083 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02639 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/66795

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. An epitaxial film is formed over a semiconductor fin, and the epitaxial film includes a top surface having two facets. A cap layer is deposited on the top surface, and portions of the epitaxial film in a lateral direction are removed. Having a smaller lateral dimension prevents the epitaxial film from merging with an adjacent epitaxial film and creates a gap between the epitaxial film and the adjacent epitaxial film.

Abstract translation: 提供了诸如FinFET的半导体器件的形成方法。 在半导体翅片上形成外延膜，外延膜包括具有两个面的顶面。 覆盖层沉积在顶表面上，并且外延膜的横向方向的部分被去除。 具有较小的横向尺寸防止外延膜与相邻的外延膜合并并在外延膜和相邻的外延膜之间产生间隙。

公开(公告)号：US20140106547A1

公开(公告)日：2014-04-17

申请号：US14133148

申请日：2013-12-18

Applicant: APPLIED MATERIALS, INC.

Inventor： Zhiyuan YE ,  Xuebin LI ,  Saurabh CHOPRA ,  Yihwan KIM

IPC: H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/0257 ,  H01L21/02576 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/78

Abstract: Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a silicon epitaxial layer on a substrate at increased pressure and reduced temperature. The silicon epitaxial layer has a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, and is formed without the addition of carbon. A phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater increases the tensile strain of the deposited layer, and thus, improves channel mobility. Since the epitaxial layer is substantially free of carbon, the epitaxial layer does not suffer from film formation and quality issues commonly associated with carbon-containing epitaxial layers.

Abstract translation: 本发明的实施例一般涉及在半导体器件上形成硅外延层的方法。 所述方法包括在增加的压力和降低的温度下在衬底上形成硅外延层。 硅外延层的磷浓度约为1×1021原子/立方厘米或更大，并且不添加碳形成。 大约1×1021原子/立方厘米或更大的磷浓度增加沉积层的拉伸应变，从而提高通道迁移率。 由于外延层基本上不含碳，外延层不会受到成膜和通常与含碳外延层相关的质量问题的影响。

公开(公告)号：US20160013274A1

公开(公告)日：2016-01-14

申请号：US14794914

申请日：2015-07-09

Applicant: Applied Materials, Inc.

Inventor： Abhishek DUBE ,  Yihwan KIM ,  Xuebin LI

IPC: H01L29/167 ,  H01L21/3065 ,  H01L21/223 ,  H01L21/02

CPC classification number: H01L21/02579 ,  C23C16/24 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/32135

Abstract: A method for forming a film on a substrate is provided. The method includes positioning a substrate within a processing volume of a process chamber and heating the substrate. The method further includes forming a semiconductor film on the substrate by exposing the substrate to two or more reactants including a silicon source and a halogenated dopant source. The semiconductor film includes one or more epitaxial regions and one or more non-epitaxial regions.

Abstract translation: 提供了在基板上形成膜的方法。 该方法包括将衬底定位在处理室的处理体积内并加热衬底。 该方法还包括通过将衬底暴露于包括硅源和卤化掺杂剂源的两种或更多种反应物来在衬底上形成半导体膜。 半导体膜包括一个或多个外延区和一个或多个非外延区。

公开(公告)号：US20150079803A1

公开(公告)日：2015-03-19

申请号：US14465330

申请日：2014-08-21

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau HUANG ,  Yihwan KIM

IPC: H01L21/02

CPC classification number: H01L21/02587 ,  H01L21/0237 ,  H01L21/02373 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02524 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02554 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/67115

Abstract: Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects.

Abstract translation: 本文描述的实施方案一般涉及在具有不同晶格常数的另一半导体衬底上生长的薄半导体膜中的松弛应变的方法。 应变弛豫通常包括在半导体衬底上形成应变松弛缓冲层，用于在顶部进一步生长另一半导体材料。 尽管常规形成的缓冲层通常是粗的，粗糙的和/或缺陷的，但是使用本文所述的实施方案形成的应变弛豫缓冲层表现出具有最小缺陷的改进的表面形态。