公开(公告)号：US20250149349A1

公开(公告)日：2025-05-08

申请号：US18500707

申请日：2023-11-02

Applicant: Applied Materials, Inc.

Inventor： Zuoming ZHU ,  Shu-Kwan LAU ,  Errol Antonio C. SANCHEZ ,  Abhishek DUBE ,  Ala MORADIAN

IPC: H01L21/67

Abstract: Embodiments of the present disclosure relate to multi-flow methods and related apparatus applicable for semiconductor manufacturing. In one or more embodiments, a method of substrate processing includes flowing a first gas flow into a first set of flow levels of a processing chamber, and flowing a second gas flow into a second set of flow levels of the processing chamber simultaneously with the flowing of the first gas flow. The first set of flow levels and the second set of flow levels alternate with respect to each other. The method includes heating one or more substrates positioned in the processing chamber.

公开(公告)号：US20240141498A1

公开(公告)日：2024-05-02

申请号：US18085402

申请日：2022-12-20

Applicant: Applied Materials, Inc.

Inventor： Zuoming ZHU ,  Ala MORADIAN ,  Shu-Kwan LAU ,  Manjunath SUBBANNA ,  Errol Antonio C. SANCHEZ ,  Abhishek DUBE ,  Erika R. WARRICK ,  Martin Jeffrey SALINAS ,  Chandra MOHAPATRA

IPC: C23C16/52 ,  C23C16/448 ,  C23C16/455

CPC classification number: C23C16/52 ,  C23C16/4481 ,  C23C16/45561

Abstract: The present disclosure relates to methods of correlating zones of processing chambers, and related systems and methods. In one implementation, a method of correlating zones of a processing chamber includes partitioning the processing volume into a plurality of zones along a first direction of the processing volume and a second direction of the processing volume. The second direction intersects the first direction. The plurality of zones have a first zone number (m), and a second zone number (n). The method includes determining a group number. The determining of the group number includes multiplying a first value by a second value. The first value correlates to a first zone number (m) of a plurality of zones and the second value correlates to a second zone number (n) of the plurality of zones. The method includes grouping the zones into groups having a number that is equal to the group number.

公开(公告)号：US20240038531A1

公开(公告)日：2024-02-01

申请号：US18098547

申请日：2023-01-18

Applicant: Applied Materials, Inc.

Inventor： Thomas KIRSCHENHEITER ,  John TOLLE ,  Abhishek DUBE ,  Maribel MALDONADO-GARCIA

IPC: H01L21/02 ,  H01L21/304 ,  H10B12/00

CPC classification number: H01L21/02532 ,  H01L21/02507 ,  H01L21/0245 ,  H01L21/0206 ,  H01L21/02381 ,  H01L21/0262 ,  H01L21/304 ,  H10B12/02 ,  H10B12/30

Abstract: A method and apparatus for forming strain relaxed buffers that may be used in semiconductor devices incorporating superlattice structures are provided. The method includes epitaxially depositing a first silicon germanium layer over the substrate. The first silicon germanium layer has a first surface that contacts a frontside surface of the substrate and a second surface opposite the first surface. The first silicon germanium layer has a first thickness and a germanium concentration gradient that increases from the first surface to the second surface. The method further includes epitaxially depositing a silicon germanium capping layer on the first silicon germanium layer. The silicon germanium capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient.

公开(公告)号：US20220238650A1

公开(公告)日：2022-07-28

申请号：US17231087

申请日：2021-04-15

Applicant: Applied Materials, Inc.

Inventor： Chen-Ying WU ,  Abhishek DUBE ,  Yi-Chiau HUANG

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/167 ,  H01L21/02 ,  H01L21/225

Abstract: A method for the selective formation of epitaxial layers is described herein. In the method, epitaxial layers are deposited to form source and drain regions around a horizontal gate all around (hGAA structure). The method includes co-flowing a combination of chlorinated silicon containing precursors, antimony containing precursors, and n-type dopant precursors. The resulting source and drain regions are selectively grown from crystalline nanosheets or nanowires of the hGAA structure over the non-crystalline gate structure and dielectric layers. The source and drain regions are predominantly grown in a direction.

公开(公告)号：US20180190489A1

公开(公告)日：2018-07-05

申请号：US15661124

申请日：2017-07-27

Applicant: Applied Materials, Inc.

Inventor： Xuebin LI ,  Hua CHUNG ,  Flora Fong-Song CHANG ,  Schubert S. CHU ,  Abhishek DUBE

IPC: H01L21/02 ,  H01L29/167 ,  H01L21/306 ,  C30B25/18 ,  C30B29/10 ,  C23C16/38

CPC classification number: H01L21/02639 ,  C23C16/0236 ,  C23C16/04 ,  C23C16/38 ,  C30B25/186 ,  C30B29/10 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/02614 ,  H01L21/02661 ,  H01L21/30604 ,  H01L29/167

Abstract: A method of forming a film on a substrate having silicon surfaces and dielectric surfaces includes precleaning the substrate; applying an inhibitor species to the dielectric surfaces; and exposing the substrate to a precursor while maintaining a temperature of less than about 600 degrees Celsius.

公开(公告)号：US20170098547A1

公开(公告)日：2017-04-06

申请号：US15384051

申请日：2016-12-19

Applicant: Applied Materials, Inc.

Inventor： Yihwan KIM ,  Xuebin LI ,  Abhishek DUBE

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/3083 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02639 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/66795

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. An epitaxial film is formed over a semiconductor fin, and the epitaxial film includes a top surface having two facets. A cap layer is deposited on the top surface, and portions of the epitaxial film in a lateral direction are removed. Having a smaller lateral dimension prevents the epitaxial film from merging with an adjacent epitaxial film and creates a gap between the epitaxial film and the adjacent epitaxial film.

公开(公告)号：US20160042963A1

公开(公告)日：2016-02-11

申请号：US14799387

申请日：2015-07-14

Applicant: APPLIED MATERIALS, INC.

Inventor： Yihwan KIM ,  Xuebin LI ,  Abhishek DUBE

IPC: H01L21/308 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/3083 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02639 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/66795

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. An epitaxial film is formed over a semiconductor fin, and the epitaxial film includes a top surface having two facets. A cap layer is deposited on the top surface, and portions of the epitaxial film in a lateral direction are removed. Having a smaller lateral dimension prevents the epitaxial film from merging with an adjacent epitaxial film and creates a gap between the epitaxial film and the adjacent epitaxial film.

Abstract translation: 提供了诸如FinFET的半导体器件的形成方法。 在半导体翅片上形成外延膜，外延膜包括具有两个面的顶面。 覆盖层沉积在顶表面上，并且外延膜的横向方向的部分被去除。 具有较小的横向尺寸防止外延膜与相邻的外延膜合并并在外延膜和相邻的外延膜之间产生间隙。

公开(公告)号：US20250146134A1

公开(公告)日：2025-05-08

申请号：US18500690

申请日：2023-11-02

Applicant: Applied Materials, Inc.

Inventor： Zuoming ZHU ,  Shu-Kwan LAU ,  Errol Antonio C. SANCHEZ ,  Abhishek DUBE ,  Ala MORADIAN

IPC: C23C16/52 ,  C23C16/455 ,  H01L21/67

Abstract: Embodiments of the present disclosure relate to multi-flow gas circuits, processing chambers, and related apparatus and methods applicable for semiconductor manufacturing. In one or more embodiments, a processing chamber includes a chamber body, one or more heat sources, and a gas circuit in fluid communication with the chamber body. The gas circuit includes a first flow controller and a first set of valves in fluid communication with the first flow controller. The first set of valves are in fluid communication with a first set of inject passages. The gas circuit includes a second flow controller and a second set of valves in fluid communication with the second flow controller. The second set of valves is in fluid communication with a second set of inject passages. The second set of inject passages and the first set of inject passages alternate with respect to each other along the plurality of flow levels.

公开(公告)号：US20250118576A1

公开(公告)日：2025-04-10

申请号：US18391089

申请日：2023-12-20

Applicant: Applied Materials, Inc.

Inventor： Chen-Ying WU ,  Zuoming ZHU ,  Abhishek DUBE ,  Ala MORADIAN ,  Errol Antonio C. SANCHEZ ,  Martin Jeffrey SALINAS ,  Aniketnitin PATIL ,  Raja Murali DHAMODHARAN ,  Shu-Kwan LAU

IPC: H01L21/67 ,  H01L21/02 ,  H01L21/687

Abstract: Embodiments of the present disclosure relate to chamber kits, processing chambers, and related methods and components for gas activation applicable for semiconductor manufacturing. In one or more embodiments, a processing chamber includes a chamber body and one or more heat sources configured to heat a processing volume of the chamber body. The chamber body includes one or more gas inject passages formed in the chamber body, and one or more gas exhaust passages formed in the chamber body. The processing chamber includes a first pre-heat ring that includes a first opaque surface, and a second pre-heat ring that includes a second opaque surface. The first pre-heat ring and the second pre-heat ring define a first gas flow path between the first opaque surface and the second opaque surface, and the first gas flow path in fluid communication with at least one of the one or more gas inject passages.

公开(公告)号：US20240363354A1

公开(公告)日：2024-10-31

申请号：US18636449

申请日：2024-04-16

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Raman GAIRE ,  Shi YOU ,  Pranav RAMESH ,  Houssam LAZKANI ,  Shawn THOMAS ,  Abhishek DUBE ,  Mehul B. NAIK ,  Songkram Sonny SRIVATHANAKUL

IPC: H01L21/285 ,  C30B25/18 ,  C30B29/06 ,  C30B29/68 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L21/28518 ,  C30B25/18 ,  C30B29/06 ,  C30B29/68 ,  H01L21/768 ,  H01L29/401

Abstract: Semiconductor devices and methods for manufacturing the same are provided. The method includes epitaxially growing a doped crystalline silicon-containing layer over a source/drain feature and growing a doped amorphous silicon-containing layer over a field region of a semiconductor layer. The trench is formed in the semiconductor layer and the trench exposes the source/drain feature. The method further includes epitaxially growing an undoped crystalline silicon-containing capping layer over the doped crystalline silicon-containing layer and growing an undoped amorphous silicon-containing layer over the doped silicon-containing amorphous layer. The method further includes selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer relative to the silicon-containing crystalline capping layer. The method further includes removing the silicon-containing crystalline capping layer to expose the doped silicon-containing crystalline layer.