公开(公告)号：US20050095787A1

公开(公告)日：2005-05-05

申请号：US10991460

申请日：2004-11-19

申请人： Arne Ballantine ,  Donna Johnson ,  Matthew Gallagher ,  Peter Geiss ,  Jeffrey Gilbert ,  Shwu-Jen Jeng ,  Robb Johnson

发明人： Arne Ballantine ,  Donna Johnson ,  Matthew Gallagher ,  Peter Geiss ,  Jeffrey Gilbert ,  Shwu-Jen Jeng ,  Robb Johnson

IPC分类号： C23C16/42 ,  H01L21/02 ,  H01L21/28 ,  H01L21/318 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H01L29/73 ,  H01L29/737 ,  H01L21/336

CPC分类号： H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02343 ,  H01L21/3185 ,  H01L28/20

摘要： A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.

摘要翻译： 一种在半导体衬底上形成氮化物膜的方法，包括将衬底的表面暴露于快速热处理以形成氮化物膜。

公开(公告)号：US20070207567A1

公开(公告)日：2007-09-06

申请号：US10599938

申请日：2005-04-06

申请人： Peter Geiss ,  Alvin Joseph ,  Qizhi Liu ,  Bradley Orner

发明人： Peter Geiss ,  Alvin Joseph ,  Qizhi Liu ,  Bradley Orner

IPC分类号： H01L21/04 ,  H01L29/73

CPC分类号： H01L29/0804 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

摘要： Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinsic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.

摘要翻译： 公开了一种双极互补金属氧化物半导体（BiCMOS）或NPN / PNP器件，其具有集电极，集电极之上的本征基极，与集电极相邻的浅沟槽隔离区，在本征基极之上的凸起的外部基极，T形发射极 在外部基极之上，邻近发射极的间隔物和通过间隔物与发射极分离的硅化物层。

公开(公告)号：US20050070101A1

公开(公告)日：2005-03-31

申请号：US10605435

申请日：2003-09-30

申请人： Peter Geiss ,  Alvin Joseph ,  Xuefeng Liu ,  James Nakos ,  James Quinlivan

发明人： Peter Geiss ,  Alvin Joseph ,  Xuefeng Liu ,  James Nakos ,  James Quinlivan

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/331 ,  H01L21/461

CPC分类号： H01L29/66242 ,  H01L21/31116

摘要： A method for removing silicon dioxide residuals is disclosed. The method includes reacting a portion of a silicon dioxide layer (i.e., oxide) to form a reaction product layer, removing the reaction product layer and annealing in an environment to remove oxide residuals. The method finds application in a variety of semiconductor fabrication processes including, for example, fabrication of a vertical HBT or silicon-to-silicon interface without an oxide interface.

摘要翻译： 公开了一种去除二氧化硅残留物的方法。 该方法包括使一部分二氧化硅层（即氧化物）反应以形成反应产物层，除去反应产物层并在环境中退火以除去氧化物残余物。 该方法应用于各种半导体制造工艺中，包括例如制造垂直HBT或无硅氧化物界面的硅 - 硅界面。

公开(公告)号：US06258695B1

公开(公告)日：2001-07-10

申请号：US09244959

申请日：1999-02-04

申请人： James Dunn ,  Peter Geiss ,  Stephen St. Onge

发明人： James Dunn ,  Peter Geiss ,  Stephen St. Onge

IPC分类号： H01L21762

CPC分类号： H01L21/763 ,  H01L21/76213 ,  H01L21/76237

摘要： A method of reducing the formation of silicon crystal defects due to extrinsic stresses in an integrated circuit chip. The source of such extrinsic stresses may be filling trenches with polycrystalline silicon or oxide, silicides, forming silicon nitride spacers or liners, or during oxide birds-beak formation, or at numerous other processing points. At an appropriate point, as each sensitive feature is defined or formed, carbon co-implanted into the silicon wafer at or near the feature.

摘要翻译： 一种减少由于集成电路芯片中的外在应力引起的硅晶体缺陷的形成的方法。 这种外在应力的来源可能是用多晶硅或氧化物，硅化物，形成氮化硅间隔物或衬垫填充沟槽，或者在氧化物鸟喙形成期间，或在许多其它加工点处。 在适当的点，由于每个敏感特征被定义或形成，碳在特征处或附近共同注入硅晶片。

公开(公告)号：US20060060887A1

公开(公告)日：2006-03-23

申请号：US10711482

申请日：2004-09-21

申请人： Peter Geiss ,  Alvin Joseph ,  Rajendran Krishnasamy ,  Xuefeng Liu

发明人： Peter Geiss ,  Alvin Joseph ,  Rajendran Krishnasamy ,  Xuefeng Liu

IPC分类号： H01L31/109

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions includes a first region doped with an impurity having a first concentration and a second region doped with the impurity having a second concentration. Noise performance and reliability of the heterojunction bipolar transistor is improved without degrading ac performance.

摘要翻译： 在包括集电极区域的第一导电类型的半导体衬底中形成异质结双极晶体管。 在基板上形成基极区域，在基极区域上形成发射极区域。 集电极，基极和发射极区域中的至少一个包括掺杂有第一浓度的杂质的第一区域和掺杂有第二浓度的杂质的第二区域。 提高异质结双极晶体管的噪声性能和可靠性，而不会降低交流性能。

公开(公告)号：US5685034A

公开(公告)日：1997-11-11

申请号：US606595

申请日：1996-02-26

申请人： Johannes-Konrad Kleer ,  Joachim Konig ,  Michael Hehl ,  Peter Geiss

发明人： Johannes-Konrad Kleer ,  Joachim Konig ,  Michael Hehl ,  Peter Geiss

IPC分类号： A61G7/02 ,  A61G7/00

CPC分类号： A61G7/02

摘要： A hospital bed includes a frame assembly having a two-part mattress support comprised of a head mattress support and a foot mattress support, with the head mattress support including a head portion and a horizontal ramp articulated to one another, and with the foot mattress support including an front portion and a rear portion articulated to one another. The head mattress support is movable in a horizontal direction relative to the foot mattress support and tiltable in a vertical direction while the front portion of the foot mattress support is tiltable in a vertical direction, with the rear portion of the foot matress support movable between outer and inner positions to allow formation of an opening when the rear portion of the foot mattress support is moved to inner position. An upwardly open toilet pan which is supported by the frame assembly is movable in position for vertical registry with the opening when the rear portion of the foot mattress support occupies the inner position.

摘要翻译： 医院床包括框架组件，其具有由头部床垫支撑件和脚垫床垫支撑件组成的两部分床垫支撑件，头部床垫支撑件包括彼此铰接的头部部分和水平斜面，并且与床垫支撑件 包括相互铰接的前部和后部。 头部床垫支撑件可相对于脚垫支撑件在水平方向上移动，并且可在垂直方向上倾斜，同时足部床垫支撑件的前部可在垂直方向上倾斜，而脚垫支撑件的后部可在外部 以及当足部床垫支撑件的后部移动到内部位置时允许形成开口的内部位置。 当脚垫支撑件的后部占据内部位置时，由框架组件支撑的向上打开的马桶盘可移动到适当位置，以垂直对准开口。

公开(公告)号：US20060017066A1

公开(公告)日：2006-01-26

申请号：US11231385

申请日：2005-09-21

申请人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

发明人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

IPC分类号： H01L31/109

CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。

公开(公告)号：US20070284694A1

公开(公告)日：2007-12-13

申请号：US11770993

申请日：2007-06-29

申请人： Peter Geiss ,  Joseph Greco ,  Richard Kontra ,  Emily Lanning

发明人： Peter Geiss ,  Joseph Greco ,  Richard Kontra ,  Emily Lanning

IPC分类号： H01L21/8222 ,  H01L21/331

CPC分类号： H01L29/6656 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/0804 ,  H01L29/1083 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/66242 ,  H01L29/7375 ,  H01L29/7378 ,  Y10S257/914

摘要： A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method includes forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.

摘要翻译： 调制多晶硅层的晶粒尺寸的方法和用该方法制造的器件。 该方法包括在衬底上形成多晶硅层; 并且进行多晶硅粒度调制物质的离子注入到所述多晶硅层中，使得在进行预定退火之后所述注入的多晶硅层的平均所得晶粒尺寸高于或低于平均得到的晶粒尺寸， 在多晶硅层上执行相同的预定退火，而不需要多晶粒度调节物质离子注入。

公开(公告)号：US20060124964A1

公开(公告)日：2006-06-15

申请号：US11288843

申请日：2005-11-29

申请人： Peter Geiss ,  Peter Gray ,  Alvin Joseph ,  Qizhi Liu

发明人： Peter Geiss ,  Peter Gray ,  Alvin Joseph ,  Qizhi Liu

IPC分类号： H01L31/109

CPC分类号： H01L29/0821 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66318

摘要： A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.

公开(公告)号：US20050199908A1

公开(公告)日：2005-09-15

申请号：US10708598

申请日：2004-03-13

申请人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

发明人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。