公开(公告)号：US08402404B1

公开(公告)日：2013-03-19

申请号：US13298541

申请日：2011-11-17

申请人： Ashok Mehta ,  Stanley John ,  Kai-Yuan Ting ,  Sandeep Kumar Goel ,  Chao-Yang Yeh

发明人： Ashok Mehta ,  Stanley John ,  Kai-Yuan Ting ,  Sandeep Kumar Goel ,  Chao-Yang Yeh

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/50 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

摘要： A system includes an automated place and route tool to generate a layout of an integrated circuit (IC) die based on a gate level circuit description. A machine readable persistent storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second IC dies, respectively, and a second portion encoded with a second gate level description of the plurality of circuit patterns received from the tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented verification module is provided for comparing the first and second gate level descriptions and outputting an error report if the second gate level description has an error. The verification module outputs a verified second gate-level description of the first and second circuit patterns.

摘要翻译： 一种系统包括基于门级电路描述产生集成电路（IC）裸片的布局的自动放置和布线工具。 机器可读永久存储介质分别包括第一部分，第一部分被编码为将分别形成在第一和第二IC管芯上的​​第一和第二电路图案的第一栅极级描述，以及用多个第二栅极电平描述编码的第二部分 从工具接收的电路图案。 第二门级描述包括电源和接地端口，并且第一门级描述不包括电源和接地端口。 提供了一种处理器实现的验证模块，用于比较第一和第二门级描述，并且如果第二门级描述具有错误则输出错误报告。 验证模块输出第一和第二电路图案的验证的第二门级描述。

公开(公告)号：US09704766B2

公开(公告)日：2017-07-11

申请号：US13118201

申请日：2011-05-27

申请人： Sandeep Kumar Goel ,  Mill-Jer Wang ,  Chung-Sheng Yuan ,  Tom Chen ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee

发明人： Sandeep Kumar Goel ,  Mill-Jer Wang ,  Chung-Sheng Yuan ,  Tom Chen ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee

IPC分类号： H01L23/48 ,  H01L21/66 ,  H01L25/065

CPC分类号： H01L22/32 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/00

摘要： An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.

公开(公告)号：US09817029B2

公开(公告)日：2017-11-14

申请号：US13313228

申请日：2011-12-07

申请人： Mill-Jer Wang ,  Ching-Fang Chen ,  Sandeep Kumar Goel ,  Chung-Sheng Yuan ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee ,  Hung-Chih Lin

发明人： Mill-Jer Wang ,  Ching-Fang Chen ,  Sandeep Kumar Goel ,  Chung-Sheng Yuan ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee ,  Hung-Chih Lin

IPC分类号： G01R1/067 ,  G01R1/073

CPC分类号： G01R1/07342 ,  G01R1/07378 ,  H01L2224/16225

摘要： A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

公开(公告)号：US08856710B2

公开(公告)日：2014-10-07

申请号：US13172248

申请日：2011-06-29

申请人： Chao-Yang Yeh ,  Ze-Ming Wu ,  Meng-Lin Chung ,  Chih-Chia Chen ,  Li-Fu Ding ,  Sa-Lly Liu

发明人： Chao-Yang Yeh ,  Ze-Ming Wu ,  Meng-Lin Chung ,  Chih-Chia Chen ,  Li-Fu Ding ,  Sa-Lly Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method comprises analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium. A substrate mesh model of the semiconductor interposer is generated, having a plurality of substrate mesh nodes. Each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements. A set of inputs to a timing analysis tool is formed. The plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model. The set of inputs is stored in a tangible machine readable storage medium.

摘要翻译： 一种方法包括使用机器实施的RC提取工具来分析半导体插入器上的前侧导电图案和背面导电图案，并将表示多个相应RC节点的数据从RC提取工具输出到有形的持久机器可读存储介质。 产生半导体插入器的衬底网格模型，其具有多个衬底网格节点。 每个衬底网格节点通过相应的衬底阻抗元件连接到多个衬底网格节点中的相邻衬底网格节点。 形成了一组时序分析工具的输入。 多个RC节点连接到衬底网格模型的多个衬底网格节点中的一个。 该组输入存储在有形机器可读存储介质中。

公开(公告)号：US20130007692A1

公开(公告)日：2013-01-03

申请号：US13172248

申请日：2011-06-29

申请人： Chao-Yang Yeh ,  Ze-Ming Wu ,  Meng-Lin Chung ,  Chih-Chia Chen ,  Li-Fu Ding ,  Sa-Lly Liu

发明人： Chao-Yang Yeh ,  Ze-Ming Wu ,  Meng-Lin Chung ,  Chih-Chia Chen ,  Li-Fu Ding ,  Sa-Lly Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method comprises analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium. A substrate mesh model of the semiconductor interposer is generated, having a plurality of substrate mesh nodes. Each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements. A set of inputs to a timing analysis tool is formed. The plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model. The set of inputs is stored in a tangible machine readable storage medium.

摘要翻译： 一种方法包括使用机器实施的RC提取工具来分析半导体插入器上的前侧导电图案和背面导电图案，并将表示多个相应RC节点的数据从RC提取工具输出到有形的持久机器可读存储介质。 产生半导体插入器的衬底网格模型，其具有多个衬底网格节点。 每个衬底网格节点通过相应的衬底阻抗元件连接到多个衬底网格节点中的相邻衬底网格节点。 形成了一组时序分析工具的输入。 多个RC节点连接到衬底网格模型的多个衬底网格节点中的一个。 该组输入存储在有形机器可读存储介质中。

公开(公告)号：US08269350B1

公开(公告)日：2012-09-18

申请号：US13149480

申请日：2011-05-31

申请人： Chih-Chia Chen ,  Chao-Yang Yeh ,  Meng-Lin Chung

发明人： Chih-Chia Chen ,  Chao-Yang Yeh ,  Meng-Lin Chung

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/485

CPC分类号： H01L23/49827 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L2223/6622 ,  H01L2224/131 ,  H01L2224/16165 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/014

摘要： An interconnection component includes a plurality of through-substrate vias (TSVs) penetrating through a substrate. The plurality of TSVs includes an active TSV having a first end and a second end. The first end of the active TSV is electrically coupled to a signal-providing circuit. The second end of the active TSV is electrically coupled to an additional package component bonded to the interconnection component. The plurality of TSVs further includes a dummy TSV having a first end and a second end, wherein the first end is electrically coupled to the signal-providing circuit, and wherein the second end is open ended.

摘要翻译： 互连部件包括贯穿基板的多个穿通基板通路（TSV）。 多个TSV包括具有第一端和第二端的有源TSV。 有源TSV的第一端电耦合到信号提供电路。 有源TSV的第二端电耦合到结合到互连部件的附加封装部件。 多个TSV还包括具有第一端和第二端的虚拟TSV，其中第一端电耦合到信号提供电路，并且其中第二端是开放式的。