公开(公告)号：US20130285248A1

公开(公告)日：2013-10-31

申请号：US13836807

申请日：2013-03-15

申请人： ASIA PACIFIC MICROSYSTEMS, INC.

发明人： Hung-Lin Yin ,  Jerwei Hsieh ,  Li-Yuan Lin

IPC分类号： H01L23/498 ,  H01L21/762

CPC分类号： H01L23/49866 ,  B81C1/00269 ,  B81C2203/019 ,  H01L21/50 ,  H01L21/76251 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/2747 ,  H01L2224/27614 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/32146 ,  H01L2224/32148 ,  H01L2224/32235 ,  H01L2224/32238 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/48091 ,  H01L2224/48148 ,  H01L2224/48228 ,  H01L2224/48463 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81022 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81825 ,  H01L2224/81948 ,  H01L2224/83011 ,  H01L2224/83013 ,  H01L2224/83022 ,  H01L2224/83121 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2224/83825 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/92147 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/16235 ,  H01L2924/351 ,  H01L2924/00015 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A substrate bonding method comprises the following steps. Firstly, a first substrate and a second substrate are provided, wherein a surface of the first substrate is covered by a first Ag layer and a surface of the second substrate is covered by a second Ag layer and a metallic layer from bottom to top, wherein the metallic layer comprises a first Sn layer. Secondly, a bonding process is performed by aligning the first and second substrates followed by bringing the metallic layer into contact with the first Ag layer followed by applying a load while heating to a predetermined temperature in order to form Ag3Sn intermetallic compounds. Finally, cool down and remove the load to complete the bonding process.

摘要翻译： 基板接合方法包括以下步骤。 首先，提供第一基板和第二基板，其中第一基板的表面被第一Ag层覆盖，并且第二基板的表面被从第二Ag层和从底部到顶部的金属层覆盖，其中 金属层包括第一Sn层。 其次，通过使第一和第二基板对准，然后使金属层与第一Ag层接触，然后在加热至预定温度的同时施加负载以形成Ag 3 Sn金属间化合物，进行接合工艺。 最后，冷却并清除负载以完成粘合过程。

公开(公告)号：US09676609B2

公开(公告)日：2017-06-13

申请号：US15144896

申请日：2016-05-03

申请人： Asia Pacific Microsystems, Inc.

发明人： Jerwei Hsieh

IPC分类号： H01L21/4763 ,  B81B7/00 ,  B81C1/00

CPC分类号： B81B7/0038 ,  B81B7/0058 ,  B81B2201/032 ,  B81C1/00238 ,  B81C1/00817 ,  B81C1/00825 ,  B81C2201/053 ,  B81C2201/056 ,  B81C2203/0785

摘要： An integrated MEMS device is provided. The integrated MEMS device comprises a circuit chip and a device chip. The circuit chip has a patterned first bonding layer disposed thereon, the bonding layer being composed of a conductive material/materials. The device chip has a first structural layer and a second structural layer, the first structural layer being connected to the second structural layer and the first bonding layer of the circuit chip, and being sandwiched between the second structural layer and the circuit chip. A plurality of hermetic spaces are enclosed by the first structural layer, the second structural layer, the first bonding layer and the circuit chip.

公开(公告)号：US08916449B2

公开(公告)日：2014-12-23

申请号：US13836807

申请日：2013-03-15

申请人： Asia Pacific Microsystems, Inc.

发明人： Hung-Lin Yin ,  Jerwei Hsieh ,  Li-Yuan Lin

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L23/498 ,  H01L21/762 ,  H01L23/10 ,  H01L21/50 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  B81C1/00

CPC分类号： H01L23/49866 ,  B81C1/00269 ,  B81C2203/019 ,  H01L21/50 ,  H01L21/76251 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/2747 ,  H01L2224/27614 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/32146 ,  H01L2224/32148 ,  H01L2224/32235 ,  H01L2224/32238 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/48091 ,  H01L2224/48148 ,  H01L2224/48228 ,  H01L2224/48463 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81022 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81825 ,  H01L2224/81948 ,  H01L2224/83011 ,  H01L2224/83013 ,  H01L2224/83022 ,  H01L2224/83121 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2224/83825 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/92147 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/16235 ,  H01L2924/351 ,  H01L2924/00015 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A substrate bonding method comprises the following steps. Firstly, a first substrate and a second substrate are provided, wherein a surface of the first substrate is covered by a first Ag layer and a surface of the second substrate is covered by a second Ag layer and a metallic layer from bottom to top, wherein the metallic layer comprises a first Sn layer. Secondly, a bonding process is performed by aligning the first and second substrates followed by bringing the metallic layer into contact with the first Ag layer followed by applying a load while heating to a predetermined temperature in order to form Ag3Sn intermetallic compounds. Finally, cool down and remove the load to complete the bonding process.

摘要翻译： 基板接合方法包括以下步骤。 首先，提供第一基板和第二基板，其中第一基板的表面被第一Ag层覆盖，并且第二基板的表面被从第二Ag层和从底部到顶部的金属层覆盖，其中 金属层包括第一Sn层。 其次，通过使第一和第二基板对准，然后使金属层与第一Ag层接触，然后在加热至预定温度的同时施加负载以形成Ag 3 Sn金属间化合物，进行接合工艺。 最后，冷却并清除负载以完成粘合过程。

公开(公告)号：US20130205899A1

公开(公告)日：2013-08-15

申请号：US13764780

申请日：2013-02-11

申请人： Asia Pacific Microsystems, Inc.

发明人： Chang-Wen Wu ,  Jerwei Hsieh ,  Wu-Chen Yeh ,  Hung-Lin Yin ,  Huai-Wei Hsi

IPC分类号： G01P1/00

CPC分类号： G01P1/00 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81B2201/0278 ,  G01P15/0802 ,  G01P15/123

摘要： A combo transducer includes a base, a proof mass, a membrane unit and a plurality of transducing components. The base is formed with an aperture. The proof mass is disposed in the aperture and has a surface that is formed with a cavity. The membrane unit includes a supporting part connected to the base, a covering part disposed to cover the surface of the proof mass, and a resilient linking part interconnecting the supporting part and the covering part such that the proof mass is movable relative to the base. The transducing components are disposed at the membrane unit. At least one of the transducing components is disposed at the covering part and is registered with the cavity.

摘要翻译： 组合传感器包括基座，检测质量块，膜单元和多个换能元件。 基座形成有孔。 检测体设置在孔中，并具有形成有空腔的表面。 膜单元包括连接到基座的支撑部分，设置成覆盖防弹块表面的覆盖部分和将支撑部分和覆盖部分互连的弹性连接部分，使得证明物质可相对于基部移动。 传感组件设置在膜单元处。 至少一个转换部件设置在覆盖部分并且与空腔配准。

公开(公告)号：US20160244323A1

公开(公告)日：2016-08-25

申请号：US15144896

申请日：2016-05-03

申请人： Asia Pacific Microsystems, Inc.

发明人： Jerwei Hsieh

IPC分类号： B81B7/00

CPC分类号： B81B7/0038 ,  B81B7/0058 ,  B81B2201/032 ,  B81C1/00238 ,  B81C1/00817 ,  B81C1/00825 ,  B81C2201/053 ,  B81C2201/056 ,  B81C2203/0785

摘要： An integrated MEMS device is provided. The integrated MEMS device comprises a circuit chip and a device chip. The circuit chip has a patterned first bonding layer disposed thereon, the bonding layer being composed of a conductive material/materials. The device chip has a first structural layer and a second structural layer, the first structural layer being connected to the second structural layer and the first bonding layer of the circuit chip, and being sandwiched between the second structural layer and the circuit chip. A plurality of hermetic spaces are enclosed by the first structural layer, the second structural layer, the first bonding layer and the circuit chip.

摘要翻译： 提供集成的MEMS器件。 集成MEMS器件包括电路芯片和器件芯片。 电路芯片具有设置在其上的图案化第一接合层，接合层由导电材料/材料构成。 器件芯片具有第一结构层和第二结构层，第一结构层连接到电路芯片的第二结构层和第一结合层，并夹在第二结构层和电路芯片之间。 第一结构层，第二结构层，第一结合层和电路芯片包围多个封闭空间。

公开(公告)号：US09359193B2

公开(公告)日：2016-06-07

申请号：US14165752

申请日：2014-01-28

申请人： Asia Pacific Microsystems, Inc.

发明人： Jerwei Hsieh

IPC分类号： H01L21/4763 ,  B81C1/00 ,  B81B7/00

CPC分类号： B81B7/0038 ,  B81B7/0058 ,  B81B2201/032 ,  B81C1/00238 ,  B81C1/00817 ,  B81C1/00825 ,  B81C2201/053 ,  B81C2201/056 ,  B81C2203/0785

摘要： An integrated MEMS device and its manufacturing method are provided. In the manufacturing method, the sacrificial layer is used to integrate the MEMS wafer and the circuit wafer. The advantage of the present invention comprises preventing films on the circuit wafer from being damaged during process. By the manufacturing method, a mechanically and thermally stable structure material, for example: monocrystalline silicon and polysilicon, can be used. The integrated MEMS device manufactured can also possess the merit of planar top-surface topography with high fill factor. The manufacturing method is especially suitable for manufacturing MEMS array device.

摘要翻译： 提供集成的MEMS器件及其制造方法。 在制造方法中，牺牲层用于集成MEMS晶片和电路晶片。 本发明的优点包括防止电路晶片上的膜在加工过程中被损坏。 通过制造方法，可以使用机械和热稳定的结构材料，例如：单晶硅和多晶硅。 制造的集成MEMS器件也可以具有高填充因子的平面顶表面形貌的优点。 该制造方法特别适用于制造MEMS阵列器件。

公开(公告)号：US20150274514A1

公开(公告)日：2015-10-01

申请号：US14165752

申请日：2014-01-28

申请人： Asia Pacific Microsystems, Inc.

发明人： Jerwei Hsieh

IPC分类号： B81C1/00 ,  B81B7/00

CPC分类号： B81B7/0038 ,  B81B7/0058 ,  B81B2201/032 ,  B81C1/00238 ,  B81C1/00817 ,  B81C1/00825 ,  B81C2201/053 ,  B81C2201/056 ,  B81C2203/0785

摘要： An integrated MEMS device and its manufacturing method are provided. In the manufacturing method, the sacrificial layer is used to integrate the MEMS wafer and the circuit wafer. The advantage of the present invention comprises preventing films on the circuit wafer from being damaged during process. By the manufacturing method, a mechanically and thermally stable structure material, for example: monocrystalline silicon and polysilicon, can be used. The integrated MEMS device manufactured can also possess the merit of planar top-surface topography with high fill factor. The manufacturing method is especially suitable for manufacturing MEMS array device.

摘要翻译： 提供集成的MEMS器件及其制造方法。 在制造方法中，牺牲层用于集成MEMS晶片和电路晶片。 本发明的优点包括防止电路晶片上的膜在加工过程中被损坏。 通过制造方法，可以使用机械和热稳定的结构材料，例如：单晶硅和多晶硅。 制造的集成MEMS器件也可以具有高填充因子的平面顶表面形貌的优点。 该制造方法特别适用于制造MEMS阵列器件。