公开(公告)号：US09472436B2

公开(公告)日：2016-10-18

申请号：US14273369

申请日：2014-05-08

Applicant: Brewer Science Inc.

Inventor： Rama Puligadda ,  Xing-Fu Zhong ,  Tony D. Flaim ,  Jeremy McCutcheon

IPC: H01L21/00 ,  H01L21/683 ,  H01L21/20 ,  H01L23/00 ,  B32B38/00 ,  B32B38/10 ,  B32B43/00

CPC classification number: H01L21/6835 ,  B32B38/0008 ,  B32B38/10 ,  B32B43/006 ,  H01L21/2007 ,  H01L21/6836 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T156/11 ,  Y10T156/1126 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/31511 ,  Y10T428/31551 ,  Y10T428/31663 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31935 ,  Y10T428/31938 ,  H01L2924/00

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

公开(公告)号：US20140239453A1

公开(公告)日：2014-08-28

申请号：US14273369

申请日：2014-05-08

Applicant: Brewer Science Inc.

Inventor： Rama Puligadda ,  Xing-Fu Zhong ,  Tony D. Flaim ,  Jeremy McCutcheon

IPC: H01L21/683

CPC classification number: H01L21/6835 ,  B32B38/0008 ,  B32B38/10 ,  B32B43/006 ,  H01L21/2007 ,  H01L21/6836 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T156/11 ,  Y10T156/1126 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/31511 ,  Y10T428/31551 ,  Y10T428/31663 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31935 ,  Y10T428/31938 ,  H01L2924/00

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

Abstract translation: 提供临时连接半导体衬底的多个结合层方案。 在本发明的接合方案中，至少一个层直接与半导体衬底接触，且该方案中的至少两个层彼此直接接触。 本发明提供了多个处理选择，因为多层结构内的不同层执行特定的功能。 更重要的是，它将通过提供更高的热稳定性，与苛刻的背面处理步骤的更大兼容性，通过封装保护晶片正面的凸块，在脱粘步骤中降低应力和减少剥离步骤来提高薄晶片处理解决方案的性能 正面的缺陷。

公开(公告)号：US20140174627A1

公开(公告)日：2014-06-26

申请号：US14191544

申请日：2014-02-27

Applicant: Brewer Science Inc.

Inventor： Rama Puligadda ,  Xing-Fu Zhong ,  Tony D. Flaim ,  Jeremy McCutcheon

IPC: H01L23/00

CPC classification number: H01L21/6835 ,  B32B38/0008 ,  B32B38/10 ,  B32B43/006 ,  H01L21/2007 ,  H01L21/6836 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T156/11 ,  Y10T156/1126 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/31511 ,  Y10T428/31551 ,  Y10T428/31663 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31935 ,  Y10T428/31938 ,  H01L2924/00

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

公开(公告)号：US20140225252A1

公开(公告)日：2014-08-14

申请号：US13765429

申请日：2013-02-12

Applicant: BREWER SCIENCE INC.

Inventor： Qin Lin ,  Daniel M. Sullivan ,  Tony D. Flaim ,  Yubao Wang ,  Jamie Lea Storie

IPC: H01L21/308 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A reversal lithography approach is disclosed in which dark-field features are created on microelectronic substrates using bright-field lithography processes and a pattern reversal method. A wafer stack having a patterned imaging layer is provided that has a plurality of features formed thereon. A pattern reversal composition is applied to the patterned imaging layer overcoating the features, followed by wet etch-back of partially cured portions of the composition to expose the tops of the features. The imaging layer is then removed resulting in reversal of the pattern into the pattern reversal composition. This reversed pattern is then transferred into subsequent layers

Abstract translation: 公开了一种反转光刻方法，其中使用亮场光刻工艺和图案反转方法在微电子基板上产生暗场特征。 提供具有图案化成像层的晶片叠层，其具有形成在其上的多个特征。 将图案反转组合物施加到覆盖特征的图案化成像层上，随后湿法蚀刻组合物的部分固化部分以暴露特征的顶部。 然后去除成像层，导致图案反转成图案反转组合物。 然后将该反转图案转移到随后的层中

公开(公告)号：US10103048B2

公开(公告)日：2018-10-16

申请号：US14472073

申请日：2014-08-28

Applicant: Brewer Science Inc.

Inventor： Tony D. Flaim ,  Jeremy McCutcheon

IPC: B32B38/10 ,  H01L21/683 ,  B32B37/14 ,  B32B37/30 ,  B32B43/00 ,  B32B37/24

Abstract: A process is disclosed for using two polymeric bonding material layers to bond a device wafer and carrier wafer in a way that allows debonding to occur between the two layers under low-force conditions at room temperature. Optionally, a third layer is included at the interface between the two layers of polymeric bonding material to facilitate the debonding at this interface. This process can potentially improve bond line stability during backside processing of temporarily bonded wafers, simplify the preparation of bonded wafers by eliminating the need for specialized release layers, and reduce wafer cleaning time and chemical consumption after debonding.

公开(公告)号：US09827740B2

公开(公告)日：2017-11-28

申请号：US14805898

申请日：2015-07-22

Applicant: Brewer Science Inc.

Inventor： Xiao Liu ,  Dongshun Bai ,  Tony D. Flaim ,  Xing-Fu Zhong ,  Qi Wu

IPC: B32B38/10 ,  B32B7/06 ,  B05D3/00 ,  B32B27/06 ,  B32B37/14 ,  C09D179/08 ,  H01L21/683 ,  C08G73/10

CPC classification number: B32B7/06 ,  B05D3/007 ,  B32B27/06 ,  B32B37/14 ,  B32B2255/26 ,  B32B2307/412 ,  B32B2405/00 ,  B32B2457/00 ,  C08G73/1014 ,  C08G73/1039 ,  C08G73/1067 ,  C09D179/08 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10S156/93 ,  Y10S156/941 ,  Y10T156/1158 ,  Y10T156/1917

Abstract: The invention broadly relates to release layer compositions that enable thin wafer handling during microelectronics manufacturing. Preferred release layers are formed from compositions comprising a polyamic acid or polyimide dissolved or dispersed in a solvent system, followed by curing and/or solvent removal at about 250° C. to about 350° C. for less than about 10 minutes, yielding a thin film. This process forms the release compositions into polyimide release layers that can be used in temporary bonding processes, and laser debonded after the desired processing has been carried out.

公开(公告)号：US20160023436A1

公开(公告)日：2016-01-28

申请号：US14805898

申请日：2015-07-22

Applicant: Brewer Science Inc.

Inventor： Xiao Liu ,  Dongshun Bai ,  Tony D. Flaim ,  Xing-Fu Zhong ,  Qi Wu

IPC: B32B7/06 ,  B32B37/14 ,  B32B27/06 ,  B05D3/00

CPC classification number: B32B7/06 ,  B05D3/007 ,  B32B27/06 ,  B32B37/14 ,  B32B2255/26 ,  B32B2307/412 ,  B32B2405/00 ,  B32B2457/00 ,  C08G73/1014 ,  C08G73/1039 ,  C08G73/1067 ,  C09D179/08 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10S156/93 ,  Y10S156/941 ,  Y10T156/1158 ,  Y10T156/1917

Abstract: The invention broadly relates to release layer compositions that enable thin wafer handling during microelectronics manufacturing. Preferred release layers are formed from compositions comprising a polyamic acid or polyimide dissolved or dispersed in a solvent system, followed by curing and/or solvent removal at about 250° C. to about 350° C. for less than about 10 minutes, yielding a thin film. This process forms the release compositions into polyimide release layers that can be used in temporary bonding processes, and laser debonded after the desired processing has been carried out.

Abstract translation: 本发明广泛地涉及在微电子制造期间能够实现薄晶片处理的释放层组合物。 优选的剥离层由包含溶解或分散在溶剂体系中的聚酰胺酸或聚酰亚胺的组合物形成，随后在约250℃至约350℃下固化和/或除去溶剂少于约10分钟， 薄膜。 该方法将释放组合物形成为可用于临时粘合工艺的聚酰亚胺剥离层，并且在所需的加工已经进行之后激光剥离。

公开(公告)号：US09224631B2

公开(公告)日：2015-12-29

申请号：US14191544

申请日：2014-02-27

Applicant: Brewer Science Inc.

Inventor： Rama Puligadda ,  Xing-Fu Zhong ,  Tony D. Flaim ,  Jeremy McCutcheon

IPC: H01L21/00 ,  H01L21/683 ,  H01L21/20 ,  H01L23/00 ,  B32B38/00 ,  B32B38/10 ,  B32B43/00

CPC classification number: H01L21/6835 ,  B32B38/0008 ,  B32B38/10 ,  B32B43/006 ,  H01L21/2007 ,  H01L21/6836 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T156/11 ,  Y10T156/1126 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/31511 ,  Y10T428/31551 ,  Y10T428/31663 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31935 ,  Y10T428/31938 ,  H01L2924/00

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

Abstract translation: 提供临时连接半导体衬底的多个结合层方案。 在本发明的接合方案中，至少一个层直接与半导体衬底接触，且该方案中的至少两个层彼此直接接触。 本发明提供了多个处理选择，因为多层结构内的不同层执行特定的功能。 更重要的是，它将通过提供更高的热稳定性，与苛刻的背面处理步骤的更大兼容性，通过封装保护晶片正面的凸块，在脱粘步骤中降低应力和减少剥离步骤来提高薄晶片处理解决方案的性能 正面的缺陷。

公开(公告)号：US20200257202A1

公开(公告)日：2020-08-13

申请号：US16785163

申请日：2020-02-07

Applicant: Brewer Science, Inc.

Inventor： Tony D. Flaim ,  Gu Xu ,  Jennifer S. See

IPC: G03F7/20 ,  C08G16/02 ,  C08F222/32 ,  G03F7/16

Abstract: Methods of preparing poly(cyanocinnamate)s are provided, with those involving mild conditions and resulting in a soluble polymer that is stable at room temperature and can be coated onto microelectronic substrates. The polymer includes at least one bis(cyanoacetate) monomer and at least one aromatic dialdehyde monomer. The polymer exhibits good thermal and structural properties and high absorbance in the UV range.

公开(公告)号：US10304720B2

公开(公告)日：2019-05-28

申请号：US15650535

申请日：2017-07-14

Applicant: Brewer Science Inc.

Inventor： Christina R. Matos-Perez ,  Tony D. Flaim ,  Arthur O. Southard ,  Lisa M. Kirchner ,  Deborah Blumenshine

IPC: H01L21/762 ,  B41C1/10 ,  C07C65/21 ,  C07C65/30 ,  C07C243/12 ,  C08G69/38 ,  C08G18/76 ,  C08G12/06 ,  C08G73/02 ,  C08G18/38

Abstract: Dielectric materials with optimal mechanical properties for use in laser ablation patterning are proposed. These materials include a polymer selected from the group consisting of polyureas, polyurethane, and polyacylhydrazones. New methods to prepare suitable polyacylhydrazones are also provided. Those methods involve mild conditions and result in a soluble polymer that is stable at room temperature and can be incorporated into formulations that can be coated onto microelectronic substrates. The dielectric materials exhibit high elongation, low CTE, low cure temperature, and leave little to no debris post-ablation.