Methods of forming metal nitride materials
    1.
    发明授权
    Methods of forming metal nitride materials 有权
    形成金属氮化物材料的方法

    公开(公告)号:US09177826B2

    公开(公告)日:2015-11-03

    申请号:US13364671

    申请日:2012-02-02

    摘要: Disclosed herein are various methods of forming metal nitride layers on various types of semiconductor devices. In one example, the method includes forming a layer of insulating material above a semiconducting substrate, performing a physical vapor deposition process to form a metal nitride layer above the layer of insulating material, wherein the metal nitride layer has an intrinsic as-deposited stress level, and performing at least one process operation on the metal nitride layer to reduce a magnitude of the intrinsic as-deposited stress level in the metal nitride layer.

    摘要翻译: 本文公开了在各种类型的半导体器件上形成金属氮化物层的各种方法。 在一个示例中,该方法包括在半导体衬底上形成绝缘材料层,执行物理气相沉积工艺以在绝缘材料层之上形成金属氮化物层,其中金属氮化物层具有本征沉积的应力水平 并且对金属氮化物层进行至少一个处理操作以减少金属氮化物层中本征沉积应力水平的大小。

    Methods of Forming Metal Nitride Materials
    2.
    发明申请
    Methods of Forming Metal Nitride Materials 有权
    形成金属氮化物材料的方法

    公开(公告)号:US20130203266A1

    公开(公告)日:2013-08-08

    申请号:US13364671

    申请日:2012-02-02

    IPC分类号: H01L21/31

    摘要: Disclosed herein are various methods of forming metal nitride layers on various types of semiconductor devices. In one example, the method includes forming a layer of insulating material above a semiconducting substrate, performing a physical vapor deposition process to form a metal nitride layer above the layer of insulating material, wherein the metal nitride layer has an intrinsic as-deposited stress level, and performing at least one process operation on the metal nitride layer to reduce a magnitude of the intrinsic as-deposited stress level in the metal nitride layer.

    摘要翻译: 本文公开了在各种类型的半导体器件上形成金属氮化物层的各种方法。 在一个示例中,该方法包括在半导体衬底上形成绝缘材料层,执行物理气相沉积工艺以在绝缘材料层之上形成金属氮化物层,其中金属氮化物层具有本征沉积的应力水平 并且对金属氮化物层进行至少一个处理操作以减少金属氮化物层中本征沉积应力水平的大小。

    PROCESSES FOR FORMING INTEGRATED CIRCUITS WITH POST-PATTERNING TREAMENT
    3.
    发明申请
    PROCESSES FOR FORMING INTEGRATED CIRCUITS WITH POST-PATTERNING TREAMENT 审中-公开
    用于形成具有后花纹的集成电路的方法

    公开(公告)号:US20140024213A1

    公开(公告)日:2014-01-23

    申请号:US13551872

    申请日:2012-07-18

    IPC分类号: H01L21/768 H01L21/308

    摘要: Processes for forming an integrated circuit are provided. In an embodiment, a process for forming an integrated circuit includes forming a low-k dielectric layer overlying a base substrate. An etch mask is patterned over the low-k dielectric layer. A recess is etched into the low-k dielectric layer through the etch mask to expose a recess surface within the recess. The low-k dielectric layer and the base substrate are annealed after etching. Annealing is conducted in an annealing environment, such as in an annealing furnace that provides the annealing environment. The recess surface is exposed to the annealing environment. An electrically-conductive material is deposited in the recess after annealing to form an embedded electrical interconnect.

    摘要翻译: 提供了用于形成集成电路的工艺。 在一个实施例中,用于形成集成电路的工艺包括形成覆盖在基底衬底上的低k电介质层。 在低k电介质层上图案化蚀刻掩模。 通过蚀刻掩模将凹槽蚀刻到低k电介质层中以暴露凹部内的凹陷表面。 蚀刻后的低k电介质层和基底基板退火。 退火在退火环境中进行,例如在提供退火环境的退火炉中。 凹陷表面暴露于退火环境。 导电材料在退火之后在凹槽中沉积以形成嵌入的电互连。

    Method for producing a conductive layer
    4.
    发明申请
    Method for producing a conductive layer 失效
    导电层的制造方法

    公开(公告)号:US20060128128A1

    公开(公告)日:2006-06-15

    申请号:US11296568

    申请日:2005-12-08

    IPC分类号: H01L21/20

    摘要: In a method for producing a conductive layer a substrate is provided. On the substrate, a layer comprised of at least two different metal nitrides is provided. Especially, on a surface of the substrate a first metal nitride layer, on a surface of the first metal nitride layer a second metal nitride layer, and on a surface of the second metal nitride layer a third metal nitride layer is deposited.

    摘要翻译: 在制造导电层的方法中,提供了基板。 在衬底上提供由至少两种不同的金属氮化物组成的层。 特别地,在基板的表面上,沉积第一金属氮化物层,在第一金属氮化物层的表面上具有第二金属氮化物层,并且在第二金属氮化物层的表面上沉积第三金属氮化物层。