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1.发明授权Context-dependent memory-mapped registers for transparent expansion of a register file 失效上下文相关的内存映射寄存器，用于透明扩展寄存器文件
公开(公告)号：US5926646A
公开(公告)日：1999-07-20
申请号：US927337
申请日：1997-09-11
CPC分类号： G06F9/30138 , G06F9/30112 , G06F9/30123 , G06F9/30185 , G06F9/463
摘要： A microprocessor includes an expanded set of registers in addition to the architected set of registers specified by the microprocessor architecture employed by the microprocessor. The expanded set of registers are memory-mapped within the context of the program being executed. Upon a context switch, the microprocessor saves the state of the expanded registers to the corresponding memory locations. An application program may make use of the expanded registers by assigning the most-often used operands in the program to the set of memory locations corresponding to the expanded registers. The application programmer may than code instructions which access these operands with register identifiers corresponding to the expanded registers. In one embodiment, the microprocessor implements a portion of the expanded registers instead of the entire set of expanded registers. The implemented portion of the expanded registers are accessed as register accesses, while the unimplemented portion are converted to memory accesses. The decode unit within the microprocessor may be configured to convert instructions which are coded to access the unimplemented expanded registers into memory operations to access the corresponding memory location.
摘要翻译： 微处理器除了由微处理器采用的微处理器结构指定的结构化寄存器组之外还包括一组扩展寄存器。 扩展的寄存器组在正在执行的程序的上下文中进行存储器映射。 在上下文切换时，微处理器将扩展的寄存器的状态保存到相应的存储器位置。 应用程序可以通过将程序中最经常使用的操作数分配给对应于扩展寄存器的存储器单元组来利用扩展寄存器。 应用程序员可以编码使用与扩展寄存器对应的寄存器标识符来访问这些操作数的指令。 在一个实施例中，微处理器实现扩展寄存器的一部分，而不是整个扩展寄存器组。 扩展寄存器的实现部分作为寄存器访问进行访问，而未实现的部分被转换为存储器访问。 微处理器内的解码单元可以被配置为将编码的指令转换成存取操作，以访问未实现的扩展寄存器以访问对应的存储单元。
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2.发明授权
公开(公告)号：US6151662A
公开(公告)日：2000-11-21
申请号：US982720
申请日：1997-12-02
CPC分类号： G06F9/30192 , G06F12/0862 , G06F12/0888 , G06F9/30047 , G06F9/345 , G06F9/383 , G06F2212/6028
摘要： A microprocessor assigns a data transaction type to each instruction. The data transaction type is based upon the encoding of the instruction, and indicates an access mode for memory operations corresponding to the instruction. The access mode may, for example, specify caching and prefetching characteristics for the memory operation. The access mode for each data transaction type is selected to enhance the speed of access by the microprocessor to the data, or to enhance the overall cache and prefetching efficiency of the microprocessor by inhibiting caching and/or prefetching for those memory operations. Instead of relying on data memory access patterns and overall program behavior to determine caching and prefetching operations, these operations are determined on an instruction-by-instruction basis. Additionally, the data transaction types assigned to different instruction encodings may be revealed to program developers. Program developers may use the instruction encodings (and instruction encodings which are assigned to a nil data transaction type causing a default access mode) to optimize use of processor resources during program execution.
摘要翻译： 微处理器为每个指令分配数据事务类型。 数据交易类型基于指令的编码，并且指示对应于指令的存储器操作的访问模式。 访问模式可以例如指定用于存储器操作的缓存和预取特性。 选择每个数据事务类型的访问模式以增强微处理器对数据的访问速度，或通过禁止对这些存储器操作的高速缓存和/或预取来增强微处理器的总体缓存和预取效率。 不依赖数据存储器访问模式和整体程序行为来确定高速缓存和预取操作，而是依据逐个指令来确定这些操作。 此外，分配给不同指令编码的数据事务类型可能会显示给程序开发人员。 程序开发人员可以使用指令编码（以及分配给导致默认访问模式的零数据事务类型的指令编码）来优化程序执行期间处理器资源的使用。
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3.发明授权System and method for handling exceptional instructions in a trace cache based processor 有权用于处理基于跟踪缓存的处理器中的异常指令的系统和方法公开(公告)号：US07133969B2
公开(公告)日：2006-11-07
申请号：US10676437
申请日：2003-10-01
申请人： Mitchell Alsup , Gregory William Smaus , James K. Pickett , Brian D. McMinn , Michael A. Filippo , Benjamin T. Sander
发明人： Mitchell Alsup , Gregory William Smaus , James K. Pickett , Brian D. McMinn , Michael A. Filippo , Benjamin T. Sander
CPC分类号： G06F9/3808 , G06F9/3802 , G06F9/3861 , G06F12/0875
摘要： A system may include an instruction cache, a trace cache including a plurality of trace cache entries, and a trace generator coupled to the instruction cache and the trace cache. The trace generator may be configured to receive a group of instructions output by the instruction cache for storage in one of the plurality of trace cache entries. The trace generator may be configured to detect an exceptional instruction within the group of instructions and to prevent the exceptional instruction from being stored in a same one of the plurality of trace cache entries as any non-exceptional instruction.
摘要翻译： 系统可以包括指令高速缓存，包括多个跟踪高速缓存条目的跟踪高速缓存以及耦合到指令高速缓存和跟踪高速缓存的跟踪发生器。 跟踪发生器可以被配置为接收由指令高速缓存输出的一组指令，用于存储在多个跟踪高速缓存条目之一中。 跟踪发生器可以被配置为检测指令组内的异常指令，并且防止异常指令被存储在多个跟踪高速缓存条目中的相同的一个跟踪高速缓存条目中，如任何非异常指令。
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4.发明授权Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming 有权与释放的重命名物理寄存器中的死结果数据相关联的保留标志值与指示符，以选择设置备用寄存器，以重命名公开(公告)号：US07043626B1
公开(公告)日：2006-05-09
申请号：US10676636
申请日：2003-10-01
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/384
摘要： A method and apparatus for retaining flag values when an associated data value dies. A first storage circuit includes a free list for storing physical register names (PRNs) and indications indicative of whether a physical register associated with a PRN was assigned to store a logical register result and flag results of a first instruction and a logical register result and a subsequent instruction which overwrites the logical register result but not the flags. A second storage circuit stores PRNs separate from the free list. The first and second storage circuits output first and second PRNs to a selection circuit. If the first indication (associated with the first PRN) is in a first state, the selection circuit may provide the first PRN to a mapper for assignment to a logical register. If the first indication is in a second state, the second PRN may be provided to the mapper.
摘要翻译： 一种用于在关联的数据值死亡时保持标志值的方法和装置。 第一存储电路包括用于存储物理寄存器名称（PRN）的空闲列表和指示是否分配了与PRN相关联的物理寄存器以存储逻辑寄存器结果的指示以及第一指令和逻辑寄存器结果的标志结果，以及 后续指令覆盖逻辑寄存器结果而不是标志。 第二个存储电路存储与免费列表分开的PRN。 第一和第二存储电路将第一和第二PRN输出到选择电路。 如果第一指示（与第一PRN相关联）处于第一状态，则选择电路可以将第一PRN提供给映射器以分配给逻辑寄存器。 如果第一指示处于第二状态，则可以将第二PRN提供给映射器。
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公开(公告)号：US06957319B1
公开(公告)日：2005-10-18
申请号：US10369966
申请日：2003-02-19
申请人： Brian D. McMinn , James K. Pickett
发明人： Brian D. McMinn , James K. Pickett
IPC分类号： G06F9/22
CPC分类号： G06F9/30181 , G06F9/26 , G06F9/30145 , G06F9/3017
摘要： Integrated circuits having multiple independently accessible microcode ROMs. An integrated circuit may include a microcode unit and a plurality of microcode ROMs fabricated within the same integrated circuit. The microcode unit may be configured to receive a microcoded instruction and to identify a microcode routine that corresponds to the microcoded instruction. The microcode ROMs may collectively store the microcode routines that implement the microcoded instructions of a complex instruction set, and different microcode ROMs may have different access times. At least one of the microcode ROMs may output operations included in the microcode routine in response to the microcode unit identifying the microcode routine. Microcode routines having more performance criticality may be stored in a microcode ROM having a smaller access latency than the access latency of a microcode ROM in which microcode routines having less performance criticality are stored.
摘要翻译： 具有多个可独立访问的微码ROM的集成电路。 集成电路可以包括在同一集成电路内制造的微代码单元和多个微代码ROM。 微码单元可以被配置为接收微编码指令并且识别与微编码指令相对应的微码例程。 微代码ROM可以共同地存储实现复杂指令集的微编码指令的微代码例程，并且不同的微代码ROM可以具有不同的访问时间。 微代码ROM中的至少一个可以响应于识别微代码例程的微代码单元来输出包括在微代码例程中的操作。 具有更高性能关键性的微代码例程可以存储在具有比其中存储具有较低性能关键性的微代码例程的微代码ROM的访问等待时间更短的访问等待时间的微代码ROM中。
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6.发明授权Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation 有权计算机系统包括存储器操作的优先级，并允许较高优先级的存储器操作来中断较低优先级的存储器操作公开(公告)号：US06298424B1
公开(公告)日：2001-10-02
申请号：US09522649
申请日：2000-03-10
IPC分类号： G06F1318
CPC分类号： G06F13/18
摘要： A computer system includes one or more microprocessors. The microprocessors assign a priority level to each memory operation as the memory operations are initiated. In one embodiment, the priority levels employed by the microprocessors include a fetch priority level and a prefetch priority level. The fetch priority level is higher priority than the prefetch priority level, and is assigned to memory operations which are the direct result of executing an instruction. The prefetch priority level is assigned to memory operations which are generated according to a prefetch algorithm implemented by the microprocessor. As memory operations are routed through the computer system to main memory and corresponding data transmitted, the elements involved in performing the memory operations are configured to interrupt the transfer of data for the lower priority memory operation in order to perform the data transfer for the higher priority memory operation. While one embodiment of the computer system employs at least a fetch priority and a prefetch priority, the concept of applying priority levels to various memory operations and interrupting data transfers of lower priority memory operations to higher priority memory operations may be extended to other types of memory operations, even if prefetching is not employed within a computer system. For example, speculative memory operations may be prioritized lower than non-speculative memory operations throughout the computer system.
摘要翻译： 计算机系统包括一个或多个微处理器。 微处理器在启动存储器操作时为每个存储器操作分配一个优先级。 在一个实施例中，微处理器采用的优先级包括提取优先级和预取优先级。 提取优先级高于预取优先级，并被分配给作为执行指令的直接结果的存储器操作。 预取优先级被分配给根据由微处理器实现的预取算法生成的存储器操作。 由于存储器操作通过计算机系统被路由到主存储器和相应的数据传输，执行存储器操作所涉及的元件被配置为中断低优先级存储器操作的数据传输，以执行更高优先级的数据传输 内存操作。 虽然计算机系统的一个实施例至少采用取出优先级和预取优先级，但是将优先权等级应用于各种存储器操作和中断低优先级存储器操作的数据传输到较高优先级存储器操作的概念可以扩展到其他类型的存储器 操作，即使在计算机系统内不使用预取。 例如，在整个计算机系统中，推测性存储器操作的优先级低于非推测性存储器操作。
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7.发明授权Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation 失效计算机系统包括存储器操作的优先级，并允许较高优先级的存储器操作中断较低优先级的存储器操作
公开(公告)号：US6058461A
公开(公告)日：2000-05-02
申请号：US982588
申请日：1997-12-02
IPC分类号： G06F13/18
CPC分类号： G06F13/18
摘要： A computer system includes one or more microprocessors. The microprocessors assign a priority level to each memory operation as the memory operations are initiated. In one embodiment, the priority levels employed by the microprocessors include a fetch priority level and a prefetch priority level. The fetch priority level is higher priority than the prefetch priority level, and is assigned to memory operations which are the direct result of executing an instruction. The prefetch priority level is assigned to memory operations which are generated according to a prefetch algorithm implemented by the microprocessor. As memory operations are routed through the computer system to main memory and corresponding data transmitted, the elements involved in performing the memory operations are configured to interrupt the transfer of data for the lower priority memory operation in order to perform the data transfer for the higher priority memory operation. While one embodiment of the computer system employs at least a fetch priority and a prefetch priority, the concept of applying priority levels to various memory operations and interrupting data transfers of lower priority memory operations to higher priority memory operations may be extended to other types of memory operations, even if prefetching is not employed within a computer system. For example, speculative memory operations may be prioritized lower than non-speculative memory operations throughout the computer system.
摘要翻译： 计算机系统包括一个或多个微处理器。 微处理器在启动存储器操作时为每个存储器操作分配一个优先级。 在一个实施例中，微处理器采用的优先级包括提取优先级和预取优先级。 提取优先级高于预取优先级，并被分配给作为执行指令的直接结果的存储器操作。 预取优先级被分配给根据由微处理器实现的预取算法生成的存储器操作。 由于存储器操作通过计算机系统被路由到主存储器和相应的数据传输，执行存储器操作所涉及的元件被配置为中断低优先级存储器操作的数据传输，以执行更高优先级的数据传输 内存操作。 虽然计算机系统的一个实施例至少采用取出优先级和预取优先级，但是将优先权等级应用于各种存储器操作和中断低优先级存储器操作的数据传输到较高优先级存储器操作的概念可以扩展到其他类型的存储器 操作，即使在计算机系统内不使用预取。 例如，在整个计算机系统中，推测性存储器操作的优先级低于非推测性存储器操作。
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公开(公告)号：US20100153893A1
公开(公告)日：2010-06-17
申请号：US12333050
申请日：2008-12-11
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A technique for constraint management and validation for template-based device designs is disclosed. The technique includes generating a template-level representation of an electronic device design based on a transistor-level representation of the electronic device design. The template-level representation includes one or more hierarchies of templates. Each template represents a corresponding portion of the electronic device design. The technique further includes determining constraint declarations associated with the electronic device design and verifying whether there is a functional equivalence between the template-level representation to a register-transfer-level (RTL) representation of the electronic device design. The technique additionally includes verifying whether the constraint declarations are valid and verifying the electronic device design responsive to verifying the functional equivalence and verifying the constraint declarations.
摘要翻译： 公开了一种用于基于模板的设备设计的约束管理和验证的技术。 该技术包括基于电子设备设计的晶体管级表示来生成电子设备设计的模板级表示。 模板级表示包括一个或多个模板层次结构。 每个模板表示电子设备设计的相应部分。 该技术还包括确定与电子设备设计相关联的约束声明，以及验证模板级表示与电子设备设计的寄存器传送级（RTL）表示之间是否具有功能等同性。 该技术另外包括验证约束声明是否有效并且响应于验证功能等同性并验证约束声明来验证电子设备设计。
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9.发明授权Instruction decode unit producing instruction operand information in the order in which the operands are identified, and systems including same 有权指令解码单元按照操作数被识别的顺序产生指令操作数信息，以及包括其的系统公开(公告)号：US06539470B1
公开(公告)日：2003-03-25
申请号：US09441632
申请日：1999-11-16
申请人： Eric W. Mahurin , Brian D. McMinn
发明人： Eric W. Mahurin , Brian D. McMinn
IPC分类号： G06F930
CPC分类号： G06F9/30167 , G06F9/30152 , G06F9/3816 , G06F9/382
摘要： An instruction decode unit is described including circuitry coupled to receive an instruction. The instruction identifies multiple operands, one of which is a destination operand. The circuitry responds to the instruction by producing: (i) operand codes specifying the operands, wherein the operand codes are produced in the order in which the operands are identified within the instruction, and (ii) a destination operand signal identifying the destination operand. In one embodiment, the decode unit responds to the instruction by producing the operand codes, operand address information, control signals, and the destination operand signal. A processor including the instruction decode unit is also described, as is a computer system including the processor. The instruction may include operand information which identifies the operands. The instruction may also include destination operand information which indicates which of the operands is the destination operand. The circuitry may produce the destination operand signal dependent upon the destination operand information. The instruction may be a member of an instruction set including instructions having a variable number of bytes. In one particular example, the instruction may be an x86 instruction including operand information which identifies two operands. The instruction may include a direction bit, and the value of the direction bit may indicate which of the two operands is the destination operand. In this case, the circuitry may produce the destination operand signal dependent upon the value of the direction bit.
摘要翻译： 描述了指令解码单元，其包括耦合以接收指令的电路。 该指令标识多个操作数，其中一个是目标操作数。 电路通过产生以下命令来响应该指令：（i）指定操作数的操作数代码，其中操作数代码以指令内的操作数被识别的顺序产生，以及（ii）标识目的地操作数的目的地操作数信号。 在一个实施例中，解码单元通过产生操作数代码，操作数地址信息，控制信号和目的地操作数信号来响应该指令。 还描述了包括指令解码单元的处理器，以及包括处理器的计算机系统。 指令可以包括标识操作数的操作数信息。 指令还可以包括指示哪个操作数是目的地操作数的目的地操作数信息。 电路可以根据目的地操作数信息产生目的地操作数信号。 指令可以是包括具有可变字节数的指令的指令集的成员。 在一个特定示例中，该指令可以是包括标识两个操作数的操作数信息的x86指令。 指令可以包括方向位，并且方向位的值可以指示两个操作数中的哪一个是目的地操作数。 在这种情况下，电路可以根据方向位的值产生目标操作数信号。
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10.发明授权Configuration and method for testing a delay chain within a microprocessor clock generator 失效用于测试微处理器时钟发生器内的延迟链的配置和方法
公开(公告)号：US5430394A
公开(公告)日：1995-07-04
申请号：US212037
申请日：1994-03-11
申请人： Brian D. McMinn , Stephen C. Horne
发明人： Brian D. McMinn , Stephen C. Horne
IPC分类号： G01R31/28 , G01R31/30 , G06F1/04 , G06F1/06 , G06F11/22 , G06F15/78 , H03K3/02 , H03K5/13 , H03H11/26 , H03J1/04
摘要： A test configuration is provided which allows a plurality of variable delay units within a delay chain of a microprocessor clock generator to be compared with respect to one another. During normal operation, a set of multiplexers interposed within the delay chain are configured such that the plurality of variable delay units are electrically coupled in series with respect to one another. An external command signal may be provided to the microprocessor to initiate a test operation in which the variable delay units are tested for possible defects. During the test operation, a control unit selects the multiplexers such that the four delay units are electrically separated from one another. A common test signal is then driven through two or more of the variable delay units simultaneously, and a compare circuit coupled to the output of each variable delay unit determines whether a transition in the common pulse signal propagated through each variable delay unit at essentially the same time. If no manufacturing defects are present, the four outputs of the variable delay units should be virtually indistinguishable from one another. The results of the compare operation may be driven on external pins of the microprocessor or may be processed internally within the microprocessor. Similar tests may be conducted throughout the entire operating range of the variable delay units.
摘要翻译： 提供了一种测试配置，其允许将微处理器时钟发生器的延迟链内的多个可变延迟单元相对于彼此进行比较。 在正常操作期间，插入在延迟链内的一组多路复用器被配置为使得多个可变延迟单元相对于彼此串联电耦合。 可以向微处理器提供外部命令信号以启动测试操作，其中可变延迟单元被测试可能的缺陷。 在测试操作期间，控制单元选择多路复用器使得四个延迟单元彼此电分离。 然后，通过两个或多个可变延迟单元同时驱动公共测试信号，并且耦合到每个可变延迟单元的输出的比较电路确定通过每个可变延迟单元传播的公共脉冲信号中的转变是否基本相同 时间。 如果不存在制造缺陷，则可变延迟单元的四个输出应该几乎不能彼此区分。 比较操作的结果可以在微处理器的外部引脚上驱动，或者可以在微处理器内部进行处理。 类似的测试可以在可变延迟单元的整个操作范围内进行。
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