Milling cutter
    1.
    发明申请
    Milling cutter 有权
    铣刀

    公开(公告)号:US20070041797A1

    公开(公告)日:2007-02-22

    申请号:US10539599

    申请日:2004-12-01

    IPC分类号: B23C5/20

    摘要: The object of this invention is to provide a milling cutter which includes a cutting insert (120), which has a hexahedral shape and is provided with first and second cutting blade parts on opposite ends thereof, and a cutter body (110) provided with a plurality of insert seats (112) which the cutting insert (120) is seated in and fastened to in either of two directions. The cutting insert (120) is fastened to the associated insert seat (112) in a selected direction, thus all corner blades or main blades, provided on the first and second cutting blade parts of the cutting insert, can be used for machining workpieces. Therefore, the present invention extends the lifetime of the cutting insert (120).

    摘要翻译: 本发明的目的是提供一种铣刀,其包括具有六面体形状的切削刀片(120),并且在其相对端上设置有第一和第二切割刀片部分,以及刀具本体(110),其设置有 多个插入座(112),其中所述切削刀片(120)位于两个方向中并被紧固在两个方向上。 切削刀片(120)沿着选定的方向紧固到相关联的刀片座(112),因此设置在切削刀片的第一和第二切削刀片部分上的所有角刀片或主刀片可用于加工工件。 因此,本发明延长了切削刀片(120)的寿命。

    Method for forming a contact in semiconductor device
    2.
    发明申请
    Method for forming a contact in semiconductor device 审中-公开
    在半导体器件中形成接触的方法

    公开(公告)号:US20050142886A1

    公开(公告)日:2005-06-30

    申请号:US11026288

    申请日:2004-12-30

    摘要: A method for forming a contact hole in a semiconductor device is disclosed. The method for forming a contact hole in a semiconductor device comprises depositing a nitride layer and an ILD on a substrate including predetermined devices; forming a first photoresist pattern on the ILD and making a via hole by using the first photoresist pattern; performing a first ashing process; forming a second photoresist pattern on the ILD and making a trench using the second photoresist pattern; conducting a PET; performing a second ashing process and etching the predetermined portion of the nitride layer exposed through the via hole; and wet-cleaning the resulting structure. Accordingly, the present disclosure can fabricate a contact hole maximizing the characteristics of a semiconductor device just by performing a Post Etching Treatment after a trench is formed.

    摘要翻译: 公开了一种在半导体器件中形成接触孔的方法。 在半导体器件中形成接触孔的方法包括:在包括预定的器件的衬底上沉积氮化物层和ILD; 在ILD上形成第一光致抗蚀剂图案,并通过使用第一光致抗蚀剂图案形成通孔; 执行第一个灰化过程; 在所述ILD上形成第二光致抗蚀剂图案,并使用所述第二光致抗蚀剂图案形成沟槽; 进行PET; 执行第二灰化处理并蚀刻通过通孔露出的氮化物层的预定部分; 并湿法清洗所得到的结构。 因此,本公开可以仅在通过在形成沟槽之后执行后蚀刻处理来制造使半导体器件的特性最大化的接触孔。

    System and shadow circuits with output joining circuit
    3.
    发明申请
    System and shadow circuits with output joining circuit 有权
    具有输出接合电路的系统和阴影电路

    公开(公告)号:US20060168489A1

    公开(公告)日:2006-07-27

    申请号:US11044826

    申请日:2005-01-26

    IPC分类号: G01R31/28

    CPC分类号: G01R31/318541

    摘要: In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal in response the data input signal and the at least one system clock signal; and an output joining circuit coupled to at least the first output terminal and the second output terminal.

    摘要翻译: 在一个实施例中,一种装置包括适于在第一输出端产生响应于数据输入信号和至少一个系统时钟信号的第一输出信号的系统电路; 阴影电路,其适于在第二输出端产生响应于所述数据输入信号和所述至少一个系统时钟信号的第二输出信号; 以及耦合到至少第一输出端子和第二输出端子的输出接合电路。

    Test pattern of CMOS image sensor and method of measuring process management using the same
    4.
    发明申请
    Test pattern of CMOS image sensor and method of measuring process management using the same 失效
    CMOS图像传感器的测试图案和使用其的测量过程管理方法

    公开(公告)号:US20070080347A1

    公开(公告)日:2007-04-12

    申请号:US11545462

    申请日:2006-10-11

    申请人: Eun Cho Kee Kim

    发明人: Eun Cho Kee Kim

    IPC分类号: H01L23/58

    摘要: The test pattern according to the present invention consists of an opaque metal film pattern formed on a semiconductor substrate, an insulating film formed on the semiconductor substrate and the metal film pattern, a red color filter formed on the insulating film, a planarization layer formed on the insulating film and the red color filter, and a number of micro-lenses formed on the planarization layer.

    摘要翻译: 根据本发明的测试图案包括形成在半导体衬底上的不透明金属膜图案,形成在半导体衬底上的绝缘膜和金属膜图案,形成在绝缘膜上的红色滤色器,形成在绝缘膜上的平坦化层 绝缘膜和红色滤色器以及形成在平坦化层上的多个微透镜。

    Intervertebral disc prosthesis
    5.
    发明申请
    Intervertebral disc prosthesis 有权
    椎间盘假体

    公开(公告)号:US20070073404A1

    公开(公告)日:2007-03-29

    申请号:US11341007

    申请日:2006-01-27

    IPC分类号: A61F2/44

    摘要: The invention relates to an intervertebral disc prosthesis comprising at least two plates, namely first and second plates, articulated about each other by means of a curved surface, namely articulation, of at least one of the plates, each of the plates comprising a surface known as a contact surface, intended to be in contact with a vertebral plate of one of the vertebrae between which the prosthesis is intended to be inserted, this contact surface for each of the plates comprising a geometrical centre at equal distance from at least two diametrically opposite points located on the periphery of the plate, in which the geometric centres of the plates are not vertically aligned, this off-setting of the geometrical centres of the plates engendering an off-setting of the edges of the plates in at least one direction perpendicular to the vertical axis of the spinal column.

    摘要翻译: 本发明涉及一种椎间盘假体,其包括至少两个板,即第一和第二板,通过至少一个板的弯曲表面(即铰接)彼此铰接,每个板包括已知的表面 作为接触表面,旨在与要在其中插入假体的椎骨之一的椎板接触,每个板的该接触表面包括与至少两个直径相对的等距离的几何中心 位于板的周边的点,其中板的几何中心不垂直对准,板的几何中心的偏移设计使得板的边缘在垂直于至少一个方向上的偏移设定 到脊柱的垂直轴。

    Error detecting circuit
    6.
    发明申请
    Error detecting circuit 失效
    错误检测电路

    公开(公告)号:US20060005091A1

    公开(公告)日:2006-01-05

    申请号:US10882523

    申请日:2004-06-30

    IPC分类号: G01R31/28

    摘要: In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.

    摘要翻译: 在一个实施例中,一种装置包括数据路径电路,用于响应于数据输入信号和至少第一数据时钟信号而产生数据输出信号; 阴影电路,耦合到数据路径电路,以在功能操作模式期间响应于数据输入信号和至少第二数据时钟信号产生阴影输出信号,并且响应于扫描信号产生扫描输出信号, 在测试操作模式期间的信号和至少第一测试时钟信号; 以及耦合到数据路径和阴影电路的误差检测电路,以响应于数据输出信号和阴影输出信号之间的失配而产生误差信号。

    Analog buffer circuit for liquid crystal display device
    9.
    发明申请
    Analog buffer circuit for liquid crystal display device 有权
    液晶显示装置的模拟缓冲电路

    公开(公告)号:US20050001799A1

    公开(公告)日:2005-01-06

    申请号:US10875733

    申请日:2004-06-25

    申请人: Kee Kim

    发明人: Kee Kim

    IPC分类号: G09G3/36

    摘要: An analog buffer circuit for a liquid crystal display (LCD) device includes a first capacitor and an inverter connected in series between an input terminal and an output terminal, a first reset switch connected between the input terminal and the first capacitor to reset the first capacitor, a first feedback switch connected to a first node between the first capacitor and the first reset switch, a second capacitor and a second feedback switch connected in series between a second node and a third node, the second node connected between the first capacitor and the inverter, and the third node connected between the inverter and the output terminal, a second reset switch connected between the second node and the third node to reset the inverter, and a third reset switch connected to a fourth node between the second capacitor and the second feedback switch to reset the second capacitor.

    摘要翻译: 一种用于液晶显示器(LCD)器件的模拟缓冲电路,包括串联连接在输入端和输出端之间的第一电容器和反相器,连接在输入端和第一电容器之间的第一复位开关,以复位第一电容器 连接到第一电容器和第一复位开关之间的第一节点的第一反馈开关,串联连接在第二节点和第三节点之间的第二电容器和第二反馈开关,第二节点连接在第一电容器和第二电容器之间, 逆变器和连接在逆变器和输出端子之间的第三节点,连接在第二节点和第三节点之间的第二复位开关以复位反相器;以及第三复位开关,连接到第二电容器和第二电容器之间的第四节点 反馈开关复位第二个电容。

    Dual band antenna unit for mobile device

    公开(公告)号:US20080024372A1

    公开(公告)日:2008-01-31

    申请号:US11647022

    申请日:2006-12-28

    IPC分类号: H01Q1/24

    摘要: A dual band antenna unit for a mobile device may include an antenna receiving part, a first antenna part having a first contact point and a second contact point, a second antenna part, a first feed point and a second feed point. The second antenna part may be formed integrally with the first antenna part and may extend from the first antenna part. The second antenna part may be extractably and retractably mounted in the mobile device. The first antenna part and the second antenna part may have resonant frequencies of different frequency bands. When the second antenna part is extracted, the first contact point may contact the first feed point. When the second antenna part is retracted, the second contact point may contact the second feed point. The mobile device may operate in different frequency bands using a single antenna unit, thereby allowing freedom of internal design and meeting the demand for miniaturization.