公开(公告)号：US12108591B2

公开(公告)日：2024-10-01

申请号：US17458992

申请日：2021-08-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yiming Zhu ,  Erxuan Ping

IPC: H10B12/00 ,  H01L29/06

CPC classification number: H10B12/312 ,  H01L29/0649 ,  H10B12/482

Abstract: A method for forming a semiconductor structure includes: providing a substrate, where a sacrificial layer and an active layer located on the sacrificial layer are formed on the substrate; patterning the active layer and the sacrificial layer to form a groove, where the active layer and the sacrificial layer are divided into a plurality of active regions by the groove; forming a first isolation layer surrounding the active regions in the groove; patterning the active layer in the active regions to form a plurality of separate active patterns, where at least one of side walls or ends of the active patterns is connected to the first isolation layer; removing the sacrificial layer along an opening located between two adjacent one of the active patterns to form a gap between a bottom of the active patterns and the semiconductor substrate; and forming a bit line in the gap.

公开(公告)号：US11887859B2

公开(公告)日：2024-01-30

申请号：US17372878

申请日：2021-07-12

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Erxuan Ping ,  Zhen Zhou ,  Yanghao Liu

IPC: H01L21/308 ,  H10B12/00

CPC classification number: H01L21/3086 ,  H10B12/053 ,  H10B12/34

Abstract: A method for forming an active region array and a semiconductor structure are provided. The method for forming the active region array includes the steps of: providing a substrate; forming a first mask layer on a surface of the substrate, a first etched pattern being provided in the first mask layer; forming a second mask layer covering a surface of the first mask layer; forming a third mask layer having a second etched pattern on a surface of the second mask layer; forming a flank covering a sidewall of the second etched pattern; removing the third mask layer to form a third etched pattern between adjacent flanks; etching the first mask layer along the third etched pattern to form a fourth etched pattern in the first mask layer; and etching the substrate along the first etched pattern and the fourth etched pattern, to form multiple active regions in the substrate.

公开(公告)号：US11875835B2

公开(公告)日：2024-01-16

申请号：US17310385

申请日：2020-11-20

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Baolei Wu ,  Yulei Wu ,  Xiaoguang Wang ,  Erxuan Ping

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1659

Abstract: A memory and a read and write method of memory can prevent the magnetic random-access memory (MRAM) from being easily damaged or degraded by excessive write current during use, and increase memory integration density. The memory includes: a storage unit, comprising a storage element; a source line, electrically connected to a first end of the storage element; the memory is configured to change a storage state of the storage element by a first current and a second current, the first current flowing through the storage element and the second current flowing through the source line without flowing through the storage element.

公开(公告)号：US11805701B2

公开(公告)日：2023-10-31

申请号：US17310366

申请日：2020-11-11

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Erxuan Ping ,  Xiaoguang Wang ,  Baolei Wu ,  Yulei Wu

IPC: G11C11/16 ,  H10N50/01 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10N50/01 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H10B61/22 ,  H10N50/10 ,  H10N50/80

Abstract: A memory includes: a substrate, having a plurality of active regions arranged in an array and a plurality of word lines extending in a first direction, the active regions being inclined at a preset angle to the word lines, the active region having at least one access transistor; a plurality of bit lines, extending in a second direction perpendicular to the first direction; magnetic tunnel junctions, one end of the magnetic tunnel junction is electrically connected to one of bit lines and another end of the magnetic tunnel junction is electrically connected to two access transistors, the two access transistors electrically connected to the magnetic tunnel junction being located in two adjacent active regions, respectively.

公开(公告)号：US12082419B2

公开(公告)日：2024-09-03

申请号：US17444785

申请日：2021-08-10

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yiming Zhu ,  Erxuan Ping

IPC: H10B51/20 ,  G11C7/18 ,  H10B51/10

CPC classification number: H10B51/20 ,  G11C7/18 ,  H10B51/10

Abstract: A method for forming the semiconductor structure includes: providing a substrate, forming a sacrificial layer and an active layer on the sacrificial layer on the substrate; etching the active layer and the sacrificial layer to form active lines extending along a first direction; forming a first isolation layer that fills a spacing between the active lines; etching ends of the active lines to form openings, and exposing the sacrificial layer on side walls of the openings; removing the sacrificial layer along the openings, and forming gap between a bottom of the active lines and the substrate; and filling the gaps with a conductive material to form bit lines extending along the first direction.

公开(公告)号：US11895852B2

公开(公告)日：2024-02-06

申请号：US17460414

申请日：2021-08-30

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yiming Zhu ,  Erxuan Ping

IPC: H01L21/76 ,  H10B99/00 ,  H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B99/00 ,  H01L21/76877 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method for forming a semiconductor structure includes: providing a substrate, a sacrificial layer and active layer on sacrificial layer being formed on the substrate; etching the active layer and sacrificial layer up to a surface of the substrate to form a plurality of active lines arranged in parallel and extending along first direction; filling an opening located between two adjacent ones of active lines to form a first isolating layer; etching an end of active lines to form an opening hole; removing sacrificial layer along opening hole, to form a gap between a bottom of the active lines and substrate; filling a conductive material in the gap to form a bit line extending along first direction; patterning the active lines to form a plurality of separate active pillars arrayed along first direction and second direction; and forming semiconductor pillars on top surfaces of respective ones of the active pillars.

公开(公告)号：US11871562B2

公开(公告)日：2024-01-09

申请号：US17522281

申请日：2021-11-09

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Erxuan Ping ,  Zhen Zhou ,  Lingguo Zhang ,  Weiping Bai

IPC: H01L21/02 ,  H10B12/00 ,  G11C5/06

CPC classification number: H10B12/485 ,  G11C5/063 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02598 ,  H10B12/482 ,  H01L21/02609

Abstract: A method for forming a storage node contact structure and semiconductor structure are provided. The method includes providing a substrate having a surface on which bit line structures are formed; forming a groove at a part, corresponding to an active region, of bottom of the contact hole; and growing a silicon crystal from the groove in the contact hole by using an epitaxial growth process, and controlling growth rates of the silicon crystal in a first and second directions in a growth process to enable the growth rate of the silicon crystal in the first direction to be greater than the growth rate of the silicon crystal in the second direction at beginning of growth and enable the growth rate of the silicon crystal in the first direction to be equal to the growth rate of the silicon crystal in the second direction at end of the growth.