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公开(公告)号：US20180240781A1
公开(公告)日：2018-08-23
申请号：US15961865
申请日：2018-04-24
Applicant: CYNTEC CO., LTD.
Inventor： BAU-RU LU , MING-CHIA WU , SHAO WEI LU
IPC: H01L25/065 , H05K7/20 , H05K3/42 , H05K1/11 , H05K5/06 , H05K5/02 , H01L23/552 , H01L25/00 , H01L23/13 , H01L23/373 , H01L23/538 , H01L23/31 , H01L23/40 , H01L23/36 , H01L23/498 , H05K7/02
CPC classification number: H01L25/0655 , H01L23/13 , H01L23/3121 , H01L23/36 , H01L23/3735 , H01L23/4006 , H01L23/49811 , H01L23/5389 , H01L23/552 , H01L24/18 , H01L25/072 , H01L25/117 , H01L25/50 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2924/13055 , H01L2924/13091 , H05K1/115 , H05K3/42 , H05K5/0247 , H05K5/065 , H05K7/02 , H05K7/20509 , Y10T29/49117 , Y10T29/49155 , Y10T29/49165 , H01L2924/00014 , H01L2924/00
Abstract: The present invention discloses a three-dimensional package structure which can achieve a relatively high utilization of an internal space thereof, so that a size of electronic package structure can be reduced. The three-dimensional package structure comprises a first electronic component, a plurality of second electronic components and a plurality of conductive patterns. The first electronic component has a top surface and a bottom surface. The plurality of second electronic components are disposed over the top surface of the first electronic component. The plurality of conductive patterns are disposed over the plurality of second electronic components to electrically connect the plurality of second electronic components and the first electronic component.
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公开(公告)号：US20180082979A1
公开(公告)日：2018-03-22
申请号：US15823579
申请日：2017-11-28
Applicant: CYNTEC CO., LTD.
Inventor： BAU-RU LU , MING-CHIA WU , SHAO WEI LU
IPC: H01L25/065 , H05K5/02 , H01L23/552 , H01L25/00 , H05K5/06 , H05K1/11 , H05K3/42 , H05K7/02 , H05K7/20 , H01L23/538 , H01L23/498 , H01L23/40 , H01L23/373 , H01L23/36 , H01L23/13 , H01L23/31
CPC classification number: H01L25/0655 , H01L23/13 , H01L23/3121 , H01L23/36 , H01L23/3735 , H01L23/4006 , H01L23/49811 , H01L23/5389 , H01L23/552 , H01L25/50 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2924/13055 , H05K1/115 , H05K3/42 , H05K5/0247 , H05K5/065 , H05K7/02 , H05K7/20509 , Y10T29/49117 , Y10T29/49155 , Y10T29/49165 , H01L2924/00014 , H01L2924/00
Abstract: The present invention discloses a substrate where the lateral surface of the substrate is formed to expose at least one portion of a via(s) for circuit connection. The substrate comprises a plurality of insulating layers; and a plurality of conductive layers separated by the plurality of insulating layers. A first lateral surface of the substrate is formed by the plurality of conductive layers and the plurality of insulating layers. The first lateral surface of the substrate comprises at least one first portion of a first via filled with a first conductive material.
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Patent Agency Ranking
公开(公告)号：US20150181733A1
公开(公告)日：2015-06-25
申请号：US14536699
申请日：2014-11-10
Applicant: CYNTEC CO., LTD.
Inventor： BAU-RU LU , MING-CHIA WU , SHAO WEI LU
CPC classification number: H01L25/0655 , H01L23/13 , H01L23/3121 , H01L23/36 , H01L23/3735 , H01L23/4006 , H01L23/49811 , H01L23/5389 , H01L23/552 , H01L25/50 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2924/13055 , H05K1/115 , H05K3/42 , H05K5/0247 , H05K5/065 , H05K7/02 , H05K7/20509 , Y10T29/49117 , Y10T29/49155 , Y10T29/49165 , H01L2924/00014 , H01L2924/00
Abstract: The present invention discloses a three-dimensional package structure which can achieve a relatively high utilization of an internal space thereof, so that a size of electronic package structure can be reduced. The three-dimensional package structure comprises a first electronic component, a plurality of second electronic components and a plurality of conductive patterns. The first electronic component has a top surface and a bottom surface. The plurality of second electronic components are disposed over the top surface of the first electronic component. The plurality of conductive patterns are disposed over the plurality of second electronic components to electrically connect the plurality of second electronic components and the first electronic component.
Abstract translation: 本发明公开了一种三维封装结构，其可以实现其内部空间的相对高的利用，从而可以减小电子封装结构的尺寸。 三维封装结构包括第一电子部件，多个第二电子部件和多个导电图案。 第一电子部件具有顶表面和底表面。 多个第二电子部件设置在第一电子部件的顶表面上。 多个导电图案设置在多个第二电子部件上以电连接多个第二电子部件和第一电子部件。
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公开(公告)号：US20150181766A1
公开(公告)日：2015-06-25
申请号：US14492088
申请日：2014-09-22
Applicant: CYNTEC CO., LTD.
Inventor： BAU-RU LU , MING-CHIA WU , SHAO WEI LU
CPC classification number: H01L25/0655 , H01L23/13 , H01L23/3121 , H01L23/36 , H01L23/3735 , H01L23/4006 , H01L23/49811 , H01L23/5389 , H01L23/552 , H01L25/50 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2924/13055 , H05K1/115 , H05K3/42 , H05K5/0247 , H05K5/065 , H05K7/02 , H05K7/20509 , Y10T29/49117 , Y10T29/49155 , Y10T29/49165 , H01L2924/00014 , H01L2924/00
Abstract: The present invention discloses a substrate where the lateral surface of the substrate is formed to expose at least one portion of a via(s) for circuit connection. The substrate comprises a plurality of insulating layers; and a plurality of conductive layers separated by the plurality of insulating layers. A first lateral surface of the substrate is formed by the plurality of conductive layers and the plurality of insulating layers. The first lateral surface of the substrate comprises at least one first portion of a first via filled with a first conductive material.
Abstract translation: 本发明公开了一种衬底，其中形成衬底的侧表面以露出用于电路连接的通孔的至少一部分。 基板包括多个绝缘层; 以及由所述多个绝缘层分离的多个导电层。 基板的第一侧面由多个导电层和多个绝缘层形成。 衬底的第一侧表面包括填充有第一导电材料的第一通孔的至少一个第一部分。
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公开(公告)号：US20180145050A1
公开(公告)日：2018-05-24
申请号：US15876222
申请日：2018-01-22
Applicant: CYNTEC CO., LTD.
Inventor： BAU-RU LU , MING-CHIA WU , SHAO WEI LU
IPC: H01L25/065 , H05K5/02 , H01L23/552 , H01L25/00 , H05K5/06 , H05K1/11 , H05K3/42 , H05K7/02 , H05K7/20 , H01L23/538 , H01L23/498 , H01L23/40 , H01L23/373 , H01L23/36 , H01L23/13 , H01L23/31
CPC classification number: H01L25/0655 , H01L23/13 , H01L23/3121 , H01L23/36 , H01L23/3735 , H01L23/4006 , H01L23/49811 , H01L23/5389 , H01L23/552 , H01L25/50 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2924/13055 , H05K1/115 , H05K3/42 , H05K5/0247 , H05K5/065 , H05K7/02 , H05K7/20509 , Y10T29/49117 , Y10T29/49155 , Y10T29/49165 , H01L2924/00014 , H01L2924/00
Abstract: A three-dimensional package structure, comprising: a substrate; a first plurality of discrete electronic components disposed over the bottom surface of the substrate, wherein a first insulating layer is disposed over the bottom surface of the substrate to encapsulate the first plurality of discrete electronic components, wherein at least one second insulating layer is disposed over the first insulating layer, wherein a plurality of surface-mount pads are disposed on the bottom surface of the at least one second insulating layer and electrically connected to at least one via disposed in the at least one second insulating layer.
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公开(公告)号：US20150179611A1
公开(公告)日：2015-06-25
申请号：US14492085
申请日：2014-09-22
Applicant: CYNTEC CO., LTD.
Inventor： BAU-RU LU , MING-CHIA WU , SHAO WEI LU
IPC: H01L25/065 , H01L23/29 , H01L23/367 , H01L23/522 , H01L23/04 , H01L25/00 , H01L21/56 , H01L23/552 , H01L23/31 , H01L23/495
CPC classification number: H01L25/0655 , H01L23/13 , H01L23/3121 , H01L23/36 , H01L23/3735 , H01L23/4006 , H01L23/49811 , H01L23/5389 , H01L23/552 , H01L25/50 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2924/13055 , H05K1/115 , H05K3/42 , H05K5/0247 , H05K5/065 , H05K7/02 , H05K7/20509 , Y10T29/49117 , Y10T29/49155 , Y10T29/49165 , H01L2924/00014 , H01L2924/00
Abstract: The present invention discloses a three-dimensional package structure which can achieve a relatively high utilization of an internal space thereof, so that the size of electronic package structure can be reduced. The three-dimensional package structure comprises a substrate, a first plurality of discrete conductive components and a connecting structure. The substrate has a top surface and a bottom surface. The first plurality of discrete conductive components are disposed over the bottom surface of the substrate. The connecting structure is disposed over the bottom surface of the substrate for encapsulating the first plurality of discrete electronic components. The connecting structure comprises at least one insulating layer and a plurality of conductive patterns separated by the at least one insulating layer. The plurality of conductive patterns are disposed over the first plurality of discrete electronic components for electrically connecting the first plurality of discrete electronic components.
Abstract translation: 本发明公开了一种可以实现其内部空间的较高利用的三维封装结构，从而可以减小电子封装结构的尺寸。 三维封装结构包括衬底，第一多个离散导电部件和连接结构。 基板具有顶表面和底表面。 第一组多个离散导电部件设置在衬底的底表面上。 连接结构设置在基板的底表面上，用于封装第一多个分立的电子部件。 连接结构包括至少一个绝缘层和由至少一个绝缘层隔开的多个导电图案。 多个导电图案设置在第一多个分立电子部件上，用于电连接第一多个分立的电子部件。
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公开(公告)号：US20170221849A1
公开(公告)日：2017-08-03
申请号：US15485235
申请日：2017-04-12
Applicant: CYNTEC CO., LTD.
Inventor： BAU-RU LU , MING-CHIA WU
IPC: H01L23/00 , H01L23/552 , H01L21/56 , H01L23/31
CPC classification number: H01L24/24 , H01L21/56 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/5389 , H01L23/552 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/19 , H01L2224/24137 , H01L2924/1206 , H01L2924/13055 , H01L2924/13091 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H05K1/0218 , H05K3/284
Abstract: A substrateless device comprises a plurality of first conductive elements and an encapsulant. The encapsulant encapsulates the plurality of first conductive elements, wherein the locations of the plurality of first conductive elements are fixed by the encapsulant; and a plurality of terminals of the plurality of first conductive elements are exposed outside the encapsulant, wherein the plurality of first conductive elements are not supported by a substrate.
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