摘要:
Compounds of the formula I: or pharmaceutically acceptable salts thereof, wherein X, R1, R2, R3, R4 and R5 are as defined herein. Also disclosed are methods of making the compounds and using the compounds for treatment of diseases associated with LRRK2 receptor, such as Parkinson's disease.
摘要:
Compounds of the formula I: or pharmaceutically acceptable salts thereof, wherein X, R1, R2, R3, R4 and R5 are as defined herein. Also disclosed are methods of making the compounds and using the compounds for treatment of diseases associated with LRRK2 receptor, such as Parkinson's disease.
摘要:
Compounds of the formula I: or pharmaceutically acceptable salts thereof, wherein m, n. X, R1, R2, R3, R5, R6 and R7 are as defined herein. Also disclosed are methods of making the compounds and using the compounds for treatment of diseases associated with LRRK2 receptor, such as Parkinson's disease.
摘要:
Compounds of the formula I: or pharmaceutically acceptable salts thereof, wherein m, n. X, R1, R2, R3, R5, R6 and R7 are as defined herein. Also disclosed are methods of making the compounds and using the compounds for treatment of diseases associated with LRRK2 receptor, such as Parkinson's disease.
摘要:
A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
摘要:
The present invention relates to frequency dividers. The frequency divider comprises an input, a counter, a first comparator, an interconnect, and an output. The counter has a counter reset port and is configured to receive a clock signal from the input and to produce a sum signal. The first comparator is configured to receive the sum signal, to compare the sum signal to a first integer, and to produce a first comparison signal. The interconnect is configured to convey the first comparison signal from the first comparator to the counter reset port. The output coupled to the first comparator. The clock signal has a periodic waveform. The sum signal represents a first sum, which equals a number of waveforms of the clock signal received by the counter after the counter has been reset. In a first embodiment, the first integer is selectable from a set of at least three consecutive integers. In a second embodiment, a frequency of the clock signal is at least 1.5 gigahertz. A third embodiment includes the features of both the first embodiment and the second embodiment.
摘要:
Methods of processing incoming documents. The methods may comprise receiving a plurality of documents in electronic form and classifying each of the plurality of documents into at least one of a plurality of document classifications. The methods may also comprise extracting metadata from the plurality of documents. In addition, the methods may comprise executing a first workflow for processing documents classified in a first document classification selected from the plurality of document classifications and executing a second workflow for processing documents classified in a second document classification selected from the plurality of document classifications.
摘要:
A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
摘要:
A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.
摘要:
At least one method for indicating a weather condition includes indexing a storm based on two or more parameters. One of the parameters is a travel speed of the storm and a second parameter is a location of the storm. The method further includes providing a time before the storm impacts a recipient based on the travel speed of the storm and a track distance to the recipient location. The method further includes delivering the time before the storm impacts the location to the recipient.