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    Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio
    5.
    发明授权
    Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio 有权
    包含双层多孔低k电介质的互连使用不同的致孔剂来构造前者的比例

    公开(公告)号：US07723226B2

    公开(公告)日：2010-05-25

    申请号：US11654427

    申请日：2007-01-17

    申请人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

    发明人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

    摘要翻译： 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积的介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部介电层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下的孔隙密度低于顶部介电层中留下的孔密度，这导致底部介电层中较高的介电常数k。

    Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio
    6.
    发明申请
    Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio 有权
    包含双层多孔低k电介质的互连使用不同的致孔剂来构造前者的比例

    公开(公告)号：US20080171431A1

    公开(公告)日：2008-07-17

    申请号：US11654427

    申请日：2007-01-17

    申请人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

    发明人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

    摘要翻译： 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部电介质层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下比在顶部电介质层中留下的孔密度更低的孔密度，这导致底部电介质层中较高的介电值k。

    Method for modulating stresses of a contact etch stop layer
    8.
    发明授权
    Method for modulating stresses of a contact etch stop layer 有权
    用于调节接触蚀刻停止层的应力的方法

    公开(公告)号：US07629273B2

    公开(公告)日：2009-12-08

    申请号：US11523674

    申请日：2006-09-19

    申请人： Chen-Hua Yu ,  Hung Chun Tsai ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Yung-Cheng Lu

    发明人： Chen-Hua Yu ,  Hung Chun Tsai ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Yung-Cheng Lu

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/3105 ,  H01L21/823807 ,  H01L29/7843

    摘要： A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.

    摘要翻译： 一种形成半导体结构的方法包括提供包括第一器件区域的衬底，在第一器件区域中形成金属氧化物半导体（MOS）器件，在MOS器件上形成应力层，并进行后处理 调节应力层的应力。 后处理选自基本上由紫外线（UV）固化，激光固化，电子束固化及其组合组成的组。

    Method for modulating stresses of a contact etch stop layer
    10.
    发明申请
    Method for modulating stresses of a contact etch stop layer 有权
    用于调节接触蚀刻停止层的应力的方法

    公开(公告)号：US20080085607A1

    公开(公告)日：2008-04-10

    申请号：US11523674

    申请日：2006-09-19

    申请人： Chen-Hua Yu ,  Hung Chun Tsai ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Yung-Cheng Lu

    发明人： Chen-Hua Yu ,  Hung Chun Tsai ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Yung-Cheng Lu

    IPC分类号： H01L21/31

    CPC分类号： H01L21/3105 ,  H01L21/823807 ,  H01L29/7843

    摘要： A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.

    摘要翻译： 一种形成半导体结构的方法包括提供包括第一器件区域的衬底，在第一器件区域中形成金属氧化物半导体（MOS）器件，在MOS器件上形成应力层，并进行后处理 调节应力层的应力。 后处理选自基本上由紫外线（UV）固化，激光固化，电子束固化及其组合组成的组。