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10 条记录 (耗时 0.031 秒)

    Ion implant method for forming trench isolation for integrated circuit devices
    5.
    发明授权
    Ion implant method for forming trench isolation for integrated circuit devices 失效
    用于集成电路器件形成沟槽隔离的离子注入方法

    公开(公告)号：US6004864A

    公开(公告)日：1999-12-21

    申请号：US30195

    申请日：1998-02-25

    申请人： Ji-Chung Huang ,  Han-Liang Tseng ,  Chia-Hsiang Chen ,  Kuo-Sheng Chuang

    发明人： Ji-Chung Huang ,  Han-Liang Tseng ,  Chia-Hsiang Chen ,  Kuo-Sheng Chuang

    IPC分类号： H01L21/761 ,  H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76237 ,  H01L21/761 ,  Y10S148/05

    摘要： A method is described for forming trench isolation for integrated circuits on silicon wafers by selectively doping the trench regions by ion implantation and then etching these areas with a wet chemical etch. A dopant such as boron, is implanted in a sequence of energies and doses to provide a desired trench profile of heavily doped silicon. The implanted silicon etches far more rapidly than the surrounding silicon and is readily etched out forming a trench. The concentration of dopant diminishes rapidly in the periphery of the implanted region. As the etch front approaches the periphery, the silicon etch rate, likewise diminishes and the etch can be quenched to leave a uniform surface layer of enhanced boron concentration which lines the resultant trench to form an effective channel stop. Wet etched trenches provide advantages over trenches formed by RIE including smooth rounded trench profiles which reduce stress. In addition, trenches having widths below 0.25 microns and essentially vertical walls can readily be formed.

    摘要翻译： 描述了一种用于通过用离子注入选择性地掺杂沟槽区域然后用湿化学蚀刻来蚀刻这些区域来在硅晶片上形成用于集成电路的沟槽隔离的方法。 掺杂剂如硼，以能量和剂量的顺序注入，以提供重掺杂硅的期望的沟槽轮廓。 植入的硅比周围的硅蚀刻得更快，并且容易地蚀刻形成沟槽。 掺杂剂的浓度在注入区域的周围快速减少。 随着蚀刻前沿接近外围，硅蚀刻速率同样减小，蚀刻可以淬火以留下增强的硼浓度的均匀表面层，其中所述沟槽形成有效的通道阻挡。 湿蚀刻沟槽提供了优于由RIE形成的沟槽的优点，包括减少应力的平滑圆形沟槽轮廓。 此外，宽度小于0.25微米的沟槽和基本垂直的壁可容易地形成。

    Method for improved dielectric layer metrology calibration
    6.
    发明授权
    Method for improved dielectric layer metrology calibration 失效
    改进电介质层计量校准方法

    公开(公告)号：US06710889B2

    公开(公告)日：2004-03-23

    申请号：US10189052

    申请日：2002-07-02

    申请人： Pey-Yuan Lee ,  Chi-Shen Lo ,  Sian-Ren Horng ,  Han-Liang Tseng ,  Wei-Ming You ,  Yi-Hung Chen

    发明人： Pey-Yuan Lee ,  Chi-Shen Lo ,  Sian-Ren Horng ,  Han-Liang Tseng ,  Wei-Ming You ,  Yi-Hung Chen

    IPC分类号： G01B1106

    CPC分类号： G01B11/0616

    摘要： A method for measuring a dielectric layer thickness calibration reference standard including providing a substrate having a dielectric layer for calibrating a dielectric layer thickness measuring tool; cleaning the dielectric layer according to a cleaning process including at least one of spraying and scrubbing; and, measuring the thickness of the dielectric layer with the dielectric layer thickness measuring tool including at least one portion of the dielectric layer displaced from the substrate center.

    摘要翻译： 一种用于测量介电层厚度校准参考标准的方法，包括提供具有用于校准介电层厚度测量工具的介电层的衬底; 根据包括喷雾和擦洗中的至少一种的清洁过程清洁介电层; 并且用介电层厚度测量工具测量介电层的厚度，该电介质层厚度测量工具包括从衬底中心位移的电介质层的至少一部分。

    Microlens process
    7.
    发明授权
    Microlens process 失效
    微透镜工艺

    公开(公告)号：US6001540A

    公开(公告)日：1999-12-14

    申请号：US89556

    申请日：1998-06-03

    申请人： Ji-Chung Huang ,  Yea-Dean Sheu ,  Chung-En Hsu ,  Han-Liang Tseng

    发明人： Ji-Chung Huang ,  Yea-Dean Sheu ,  Chung-En Hsu ,  Han-Liang Tseng

    IPC分类号： G02B3/00 ,  G03F7/00

    CPC分类号： G02B3/0012 ,  G02B3/0056

    摘要： A process is described for forming a microlens, either directly on a substrate or as part of a process to manufacture an optical imaging array. The process starts with the deposition of a layer of silicon oxide over the substrate, said layer being the determinant of the lens to substrate distance. This is followed by layers of polysilicon and silicon nitride. The latter is patterned to form a mask which protects the poly, except for a small circular opening, during its oxidation (under the same conditions as used for LOCOS). The oxide body that is formed is lens shaped, extending above the poly surface by about the same amount as below it, and just contacting the oxide layer. After the silicon nitride and all poly have been removed, the result is a biconvex microlens. In a second embodiment, a coating of SOG is provided that has a thickness equal to half the microlens thickness, thereby converting the latter to a plano-convex lens.

    摘要翻译： 描述了用于形成微透镜的方法，其直接在衬底上或作为制造光学成像阵列的工艺的一部分。 该过程开始于在衬底上沉积一层氧化硅，所述层是透镜与衬底距离的决定因素。 之后是多晶硅层和氮化硅层。 后者被图案化以形成掩模，其在其氧化期间（在与LOCOS使用的相同条件下）保护除了小的圆形开口之外的聚合物。 形成的氧化物体是透镜形的，在聚合表面上方延伸大约与其下方相同的量，并且刚好接触氧化物层。 在氮化硅和所有聚合物被去除之后，结果是双凸透镜。 在第二实施例中，提供了SOG的涂层，其具有等于微透镜厚度的一半的厚度，从而将其转换成平凸透镜。

    System for in-line monitoring of photo processing in VLSI fabrication
    8.
    发明授权
    System for in-line monitoring of photo processing in VLSI fabrication 失效
    用于在VLSI制造中进行在线监控照相处理的系统

    公开(公告)号：US5949547A

    公开(公告)日：1999-09-07

    申请号：US803352

    申请日：1997-02-20

    申请人： Huan-Chi Tseng ,  Chia-Hsiang Chen ,  Han-Liang Tseng

    发明人： Huan-Chi Tseng ,  Chia-Hsiang Chen ,  Han-Liang Tseng

    IPC分类号： G03F7/20 ,  G03F7/207 ,  H01L23/544 ,  G01B11/14 ,  G01J1/00 ,  G01N21/86

    CPC分类号： G03F7/70641 ,  H01L22/34

    摘要： An integrated de-focus pattern provides an effective in-line monitor of de-focus and relative tilt for photo processing steps of integrated circuit wafers. The de-focus pattern is formed on an integrated circuit wafer in the vertical and horizontal spaces between integrated circuit chips. The de-focus pattern has a number of different test patterns at different heights above the wafer surface. De-focus patterns are placed across the entire wafer surface. The de-focus patterns are formed at the same time the features of the circuit chips are formed. The de-focus patterns can be analyzed optically or using a scanning electron microscope.

    摘要翻译： 集成的去焦点图案提供集成电路晶片的照相处理步骤的脱焦和相对倾斜的有效的在线监视器。 在集成电路芯片之间的垂直和水平空间中的集成电路晶片上形成去焦图案。 去焦图案在晶片表面上方的不同高度具有许多不同的测试图案。 去焦点图案放置在整个晶片表面上。 在形成电路芯片的特征的同时形成去焦图形。 去焦图案可以光学分析或使用扫描电子显微镜。

    Method for shielding polysilicon resistors from hydrogen intrusion
    9.
    发明授权
    Method for shielding polysilicon resistors from hydrogen intrusion 失效
    多晶硅电阻器防止氢侵入的方法

    公开(公告)号：US5530418A

    公开(公告)日：1996-06-25

    申请号：US507535

    申请日：1995-07-26

    申请人： Shun-Liang Hsu ,  Han-Liang Tseng ,  Mou-Shiung Lin

    发明人： Shun-Liang Hsu ,  Han-Liang Tseng ,  Mou-Shiung Lin

    IPC分类号： H01L21/02 ,  H01C1/012

    CPC分类号： H01L28/20 ,  Y10S438/926

    摘要： A polysilicon resistor structure and a method by which the polysilicon resistor structure may be formed. A polysilicon resistor is formed upon the surface of a semiconductor substrate. A pair of dummy polysilicon layers is formed along opposite edges and separated from the polysilicon resistor. A pair of metal sidewalls is then formed upon the upper surfaces of the pair of dummy polysilicon layers, and a top metal layer is formed bridging the upper surfaces of the pair of metal sidewalls. The pair of dummy polysilicon layers, the pair of metal sidewalls and the top metal layer form an open ended cavity upon the semiconductor substrate within which structure the polysilicon resistor resides. The polysilicon resistor is separated from the structure by an insulating material which is not susceptible to outgassing of hydrogen.

    摘要翻译： 多晶硅电阻结构以及可以形成多晶硅电阻结构的方法。 在半导体衬底的表面上形成多晶硅电阻器。 一对虚设多晶硅层沿着相对的边缘形成并且与多晶硅电阻器分离。 然后在一对虚设多晶硅层的上表面上形成一对金属侧壁，并且形成桥接该对金属侧壁的上表面的顶部金属层。 一对虚设多晶硅层，一对金属侧壁和顶部金属层在多晶硅电阻器所在的半导体衬底上形成开口腔。 多晶硅电阻器通过不易于逸出氢的绝缘材料与结构分离。

    System for in-line monitoring of photo processing tilt in VLSI fabrication
    10.
    发明授权
    System for in-line monitoring of photo processing tilt in VLSI fabrication 有权
    用于在VLSI制造中在线监控照片处理去焦和图像倾斜的系统

    公开(公告)号：US5990567A

    公开(公告)日：1999-11-23

    申请号：US262311

    申请日：1999-03-04

    申请人： Huan-Chi Tseng ,  Chia-Hsiang Chen ,  Han-Liang Tseng

    发明人： Huan-Chi Tseng ,  Chia-Hsiang Chen ,  Han-Liang Tseng

    IPC分类号： G03F7/20 ,  G03F7/207 ,  H01L23/544 ,  G01B11/14 ,  G01J1/00 ,  G01N21/00

    CPC分类号： G03F7/70641 ,  H01L22/34

    摘要： An integrated de-focus pattern provides an effective in-line monitor for photo processing steps of integrated circuit wafers. The de-focus pattern is formed on an integrated circuit wafer in the vertical and horizontal spaces between integrated circuit chips. The de-focus pattern has a number of different test patterns at different heights above the wafer surface. De-focus patterns are placed across the entire wafer surface. The de-focus patterns are formed at the same time the features of the circuit chips are formed. The de-focus patterns can be analyzed optically or using a scanning electron microscope.

    摘要翻译： 集成的去焦点图案为集成电路晶片的照相处理步骤提供了有效的在线监视器。 在集成电路芯片之间的垂直和水平空间中的集成电路晶片上形成去焦图案。 去焦图案在晶片表面上方的不同高度具有许多不同的测试图案。 去焦点图案放置在整个晶片表面上。 在形成电路芯片的特征的同时形成去焦图形。 去焦图案可以光学分析或使用扫描电子显微镜。