Semiconductor package with lead frame as chip carrier and method for fabricating the same
    6.
    发明授权
    Semiconductor package with lead frame as chip carrier and method for fabricating the same 失效
    具有引线框架的半导体封装作为芯片载体及其制造方法

    公开(公告)号:US07339280B2

    公开(公告)日:2008-03-04

    申请号:US10319211

    申请日:2002-12-13

    IPC分类号: H01L23/29

    摘要: A semiconductor package with a lead frame as a chip carrier and a method for fabricating the same are provided. The lead frame includes a die pad and a plurality of leads properly spaced apart from the die pad, each lead being composed of an inner lead portion and an outer lead portion, wherein the inner lead portion is directed toward the die pad, and the outer lead portion has a terminal. At least a chip is mounted on the die pad, and a first encapsulant is formed for encapsulating the chip, die pad and inner lead portions. An injection-molded second encapsulant is formed for encapsulating the first encapsulant and outer lead portions, but exposing the terminals of the outer lead portions. The second encapsulant made by injection molding can prevent resin flash over the exposed terminals, thereby assuring electrical-connection quality of the semiconductor package.

    摘要翻译: 提供了具有引线框架作为芯片载体的半导体封装及其制造方法。 引线框架包括管芯焊盘和与管芯焊盘适当间隔开的多个引线,每个引线由内引线部分和外引线部分组成,其中内引线部分指向管芯焊盘,外引线 引线部分具有端子。 至少芯片安装在管芯焊盘上,形成第一密封剂以封装芯片,管芯焊盘和内引线部分。 形成注射成型的第二密封剂,用于封装第一密封剂和外引线部分,但暴露外引线部分的端子。 通过注射成型制成的第二密封剂可以防止树脂在暴露的端子上闪烁,从而确保半导体封装的电连接质量。

    Flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same
    7.
    发明授权
    Flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same 有权
    在半导体芯片上具有专用测试焊盘的倒装凸块结构及其制造方法

    公开(公告)号:US06359342B1

    公开(公告)日:2002-03-19

    申请号:US09730311

    申请日:2000-12-05

    IPC分类号: H01L2348

    摘要: A flip-chip bumping technology is proposed, which provides a flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same. The proposed flip-chip bumping technology is characterized by the forming of a lined-array of electrically-conductive dual-pad blocks respectively over the internal I/O points of the semiconductor chip, each dual-pad block including a first pad and a second pad located beside and electrically connected to the first pad; and wherein the respective first and second pads of the dual-pad blocks-are alternately designated as bump pads and test pads. During testing procedure, the probing to the internal circuitry of the semiconductor chip is carried out through the test-pad portions of the dual-pad blocks, so that the probing needles would leave no scratches over the bumppad portions of the same. During subsequent bumping process, solder bumps are formed respectively over the bump-pad portions of the dual-pad blocks. Since the bump-pad portions of the dual-pad blocks would be left unscratched, it allows the solder bump attachment to be more assured in quality and reliability.

    摘要翻译: 提出了一种倒装芯片凸块技术,其提供了具有半导体芯片上的专用测试焊盘的倒装芯片凸块结构及其制造方法。 所提出的倒装芯片凸块技术的特征在于分别在半导体芯片的内部I / O点上形成导电双焊盘块的排列阵列,每个双焊盘块包括第一焊盘和第二焊盘 垫位于旁边并电连接到第一垫; 并且其中所述双焊盘块的相应的第一和第二焊盘被交替地指定为凸块焊盘和测试焊盘。 在测试过程中,半导体芯片的内部电路的探测通过双焊盘块的测试焊盘部分进行,使得探针不会在其上的焊盘部分上留下划痕。 在随后的凸块处理期间,分别在双焊盘块的凸块焊盘部分上形成焊料凸块。 由于双焊盘块的凸块焊盘部分将不被打开,所以允许焊料凸块附着在质量和可靠性方面更加确保。