公开(公告)号：US20070131494A1

公开(公告)日：2007-06-14

申请号：US10552386

申请日：2004-01-16

申请人： Christian Baler-Welt ,  Karlheinz Muller

发明人： Christian Baler-Welt ,  Karlheinz Muller

IPC分类号： F16D65/14

CPC分类号： B60T7/107 ,  B60T11/06 ,  B60T13/746

摘要： The invention relates to a parking brake, especially for a motor vehicle. Said parking brake (1) comprises a cable traction device in order to actuate the brake and opposite cable deflection by means of at least two deflection rollers (6, 7, 19, 20). The deflection rollers (6, 7, 19, 20) are arranged in such a manner that the connection line can be rotated between the rotational axis of at least two deflection rollers (7, 8, 19, 20) with respect to the drive main axis (18). As a result, a parking brake which is simple to construct and which requires a minimum amount of space is produced. Said parking brake can tighten two brake cables with an essentially equal force in an opposite direction.

摘要翻译： 本发明涉及一种驻车制动器，特别是用于机动车辆。 所述驻车制动器（1）包括电缆牵引装置，以便通过至少两个转向辊（6,7,19,20）致动制动器和相对的电缆偏转。 偏转辊（6,7,19,20）以这样的方式设置，使得连接线可以相对于驱动主体在至少两个偏转辊（7,8,19,20）的旋转轴线之间旋转 轴（18）。 结果，制造了简单构造并且需要最小空间的驻车制动器。 所述驻车制动器可以以相反的方向以相同的力拧紧两个制动缆索。

公开(公告)号：US6080649A

公开(公告)日：2000-06-27

申请号：US780492

申请日：1997-01-08

申请人： Wolfgang Werner ,  Karlheinz Muller ,  Holger Pohle

发明人： Wolfgang Werner ,  Karlheinz Muller ,  Holger Pohle

IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L23/58 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002

摘要： A fusible link in an integrated semiconductor circuit and a process for producing the fusible link contemplate the disposition of a fusible link, which is constructed with a cross-sectional constriction as a desired fusing point for its conductor track, in a void. A surface of the void and/or a bare conductor track can be covered with a protection layer, to prevent corrosion. The advantages of such a fusible link are a lower ignition energy and increased reliability. The fusible link may be used as a memory element of a PROM.

摘要翻译： 集成半导体电路中的可熔链路和用于制造可熔连接的工艺的过程考虑到在空隙中构造有作为其导体轨迹的期望的熔合点的横截面收缩的可熔连接件的布置。 空隙和/或裸导体轨道的表面可以用保护层覆盖，以防止腐蚀。 这种可熔连接件的优点是较低的点火能量和更高的可靠性。 可熔链路可以用作PROM的存储元件。

公开(公告)号：US5307704A

公开(公告)日：1994-05-03

申请号：US981347

申请日：1992-11-25

申请人： Karlheinz Muller ,  Peter Michel

发明人： Karlheinz Muller ,  Peter Michel

IPC分类号： E05F15/16 ,  F16H1/16 ,  F16D3/70 ,  F16H55/14

CPC分类号： F16H1/16 ,  E05F15/697 ,  E05Y2900/55 ,  Y10T74/19633 ,  Y10T74/19828

摘要： To simplify the design and assembly of an adjustment drive with a gear wheel mounted to rotate in a gear housing with a gear housing lid and with a driver provided with a power take-off element (e.g., a pinion) being in a drive connection with it on the output side, directly or indirectly, present invention provides that the driver is simultaneously structured as a power take-off shaft and is mounted to rotate with at least one bearing region in the gear housing or in the gear housing lid, respectively. In a further embodiment, the gear wheel is a one-piece component of the driver and is preferably placed into a drive connection with it via spring web type spokes in the form of tangential stop damping.

摘要翻译： 为了简化带有齿轮的调节驱动器的设计和组装，所述齿轮被安装成在具有齿轮壳体盖的齿轮壳体中旋转，并且驱动器设置有与驱动连接的动力输出元件（例如，小齿轮） 在输出侧，直接或间接地在本发明中，驱动器同时被构造为动力输出轴，并且安装成分别与齿轮箱或齿轮箱盖中的至少一个轴承区域一起旋转。 在另一个实施例中，齿轮是驱动器的一体部件，并且优选地以切向阻尼阻尼的形式经由弹簧腹板型轮辐与其一起驱动连接。

公开(公告)号：US20060125000A1

公开(公告)日：2006-06-15

申请号：US11295152

申请日：2005-12-06

申请人： Karlheinz Muller ,  Klaus Roschlau

发明人： Karlheinz Muller ,  Klaus Roschlau

IPC分类号： H01L21/8232 ,  H01L29/76

CPC分类号： H01L29/66712 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7813

摘要： A field effect transistor (FET) and fabrication method are disclosed. The FET includes a drift region formed in a substrate. A trench adjoins the drift region and contains at least one control region and a connection region. An inversion channel region is isolated from the control region. A portion of the trench extends to the same depth as a second trench that insulates the FET from other components formed in the substrate. Insulating material is disposed between the trench below the control region and the control region. An insulating layer insulates the FET from the substrate. The trench and/or the connection region may extend into the insulating layer or may be isolated from the insulating layer via the drift region.

摘要翻译： 公开了场效应晶体管（FET）和制造方法。 FET包括形成在衬底中的漂移区域。 沟槽毗邻漂移区域并且包含至少一个控制区域和连接区域。 从控制区域隔离反向沟道区域。 沟槽的一部分延伸到与第二沟槽相同的深度，该第二沟槽将FET与形成在衬底中的其它部件绝缘。 绝缘材料设置在控制区域下方的沟槽和控制区域之间。 绝缘层使FET与衬底绝缘。 沟槽和/或连接区域可以延伸到绝缘层中，或者可以经由漂移区域与绝缘层隔离。

公开(公告)号：US5444643A

公开(公告)日：1995-08-22

申请号：US117838

申请日：1993-09-08

申请人： Bernd Haussler ,  Thomas Thurner ,  Karlheinz Muller

发明人： Bernd Haussler ,  Thomas Thurner ,  Karlheinz Muller

IPC分类号： B60R16/02 ,  B60R16/03 ,  H04L12/28 ,  H04L12/40 ,  H04L12/54 ,  H04L12/861 ,  H04L12/879 ,  H04L29/08 ,  G06F9/00 ,  G06F13/00

CPC分类号： H04L49/901 ,  H04L12/40 ,  H04L12/4135 ,  H04L12/5692 ,  H04L49/90 ,  H04L49/9057 ,  B60R16/0315 ,  H04L2012/40215 ,  H04L2012/40273 ,  H04L69/324

摘要： A method for programming a bus-compatible electronic motor vehicle controller that is equipped with at least one microcomputer to implement its control function and with ROM and RAM in order to accommodate and handle applications software required for the control function, and is also equipped with at least one bus protocol chip, the ROM being programmed such that the applications software communicates with a bus via the bus protocol chip and via a specific instruction and communications interface forming a first interface of the bus protocol chip. The method includes providing a second interface, which is independent of the bus protocol chip, and defining the second interface as a further, universal instruction and communications interface. The first and second interfaces are coupled with a driver module that is independent of the applications software and adapted to the bus protocol chip and has the properties of an adapter. The applications software are matched and aligned exclusively to the second interface with respect to the bus communication and the applications software is produced independently of the bus protocol chip. The applications software and the driver module are linked to one another by a link process. Program code is obtained as a result of the link process. The program code is stored such that the program code is resident in the ROM.

摘要翻译： 一种用于编程总线兼容的电子机动车辆控制器的方法，该控制器配备有至少一个微型计算机以实现其控制功能，并且具有ROM和RAM，以便容纳和处理控制功能所需的应用软件，并且还配备 至少一个总线协议芯片，ROM被编程为使得应用软件经由总线协议芯片与总线通信，并且经由形成总线协议芯片的第一接口的特定指令和通信接口进行通信。 该方法包括提供独立于总线协议芯片的第二接口，并将第二接口定义为另外的通用指令和通信接口。 第一和第二接口与独立于应用软件的驱动器模块耦合，并适用于总线协议芯片，并具有适配器的属性。 应用软件相对于总线通信专用于第二接口，并且独立于总线协议芯片产生应用软件。 应用软件和驱动器模块通过链接过程相互链接。 作为链接过程的结果获得程序代码。 存储程序代码，使得程序代码驻留在ROM中。

公开(公告)号：US20100330765A1

公开(公告)日：2010-12-30

申请号：US12878377

申请日：2010-09-09

申请人： Karlheinz Muller ,  Klaus Roschlau

发明人： Karlheinz Muller ,  Klaus Roschlau

IPC分类号： H01L21/331

CPC分类号： H01L29/0649 ,  H01L21/2257 ,  H01L29/732 ,  H01L29/7809

摘要： Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.

摘要翻译： 公开了用于生产的集成晶体管和方法。 具体来说，说明了具有从远离主区域的连接区域的方向从主区域延伸的电绝缘隔离沟道的晶体管。 此外，晶体管包括从主区域延伸到远离主区域的连接区域的辅助沟槽。 该晶体管需要小的芯片面积并具有出色的电气特性。

公开(公告)号：US20060008933A1

公开(公告)日：2006-01-12

申请号：US10526818

申请日：2003-08-14

申请人： Karlheinz Muller ,  Johannes Sturm

发明人： Karlheinz Muller ,  Johannes Sturm

IPC分类号： H01L21/00

CPC分类号： H01L31/105 ,  H01L27/144 ,  H01L31/18

摘要： An explanation is given of, inter alia, a method for fabricating an integrated pin photodiode which contains a buried region (20) and a terminal region (32) leading to the buried region (20). This fabrication method enables the pin photodiode (14) to be integrated in a simple manner. Moreover, there is the possibility that process steps for fabricating the pin diode can also be utilized for fabricating shielding wells (22, 56).

摘要翻译： 具体地说，描述了一种制造集成pin光电二极管的方法，该方法包含埋入区域（20）和通向掩埋区域（20）的端子区域（32）。 该制造方法能够以简单的方式集成引脚光电二极管（14）。 而且，也可以利用制造pin二极管的工艺步骤来制造屏蔽阱（22,56）。

公开(公告)号：US20050118773A1

公开(公告)日：2005-06-02

申请号：US11033577

申请日：2005-01-12

申请人： Karlheinz Muller

发明人： Karlheinz Muller

IPC分类号： H01G4/33 ,  H01G4/10 ,  H01G4/30 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/1085 ,  H01L28/40

摘要： A capacitor for an integrated circuit with microstructure has a first and a second electrode separated by a dielectric layer. The dielectric layer is produced during the structuring of the first electrodes by an etching process. The dielectric layer comprises a polymer structure which is formed during the etching process, and/or etching products of the electrode metal. The first electrode may be cylindrical and surrounded by a hollow-cylindrical dielectric layer. The capacitor may be integrated in a memory field with a multiplicity of such capacitors.

摘要翻译： 具有微结构的集成电路的电容器具有由电介质层分离的第一和第二电极。 通过蚀刻工艺在第一电极的结构化期间产生电介质层。 电介质层包括在蚀刻工艺期间形成的聚合物结构和/或蚀刻电极金属的产物。 第一电极可以是圆柱形的并且被中空圆柱形介电层包围。 电容器可以集成在具有多个这种电容器的存储器场中。

公开(公告)号：US5637516A

公开(公告)日：1997-06-10

申请号：US501358

申请日：1995-07-12

申请人： Karlheinz Muller

发明人： Karlheinz Muller

IPC分类号： H01L21/8249 ,  H01L21/265

CPC分类号： H01L21/8249

摘要： A method for producing complementary MOS and bipolar transistors on the same semiconductor wafer, includes producing buried zones of differing conductivity, producing n- and p-doped wells for corresponding transistors, and producing field oxide regions and insulated gate electrodes of the MOS transistors. After production of the field oxide regions, highly doped n-regions extending from a surface of the semiconductor wafer to a buried n-doped zone are produced with a first mask for producing a collector zone of an npn transistor and a base zone of a pnp transistor. After the production of the insulated gate electrodes, a first silicon layer is applied over the entire surface and doped with p-atoms. An auxiliary layer is applied on the first silicon layer over the entire surface. The auxiliary layer and the first silicon layer are structured with a second mask. A base contact zone of the npn transistor, source and drain zones of a p-MOS transistor, and a collector zone and an emitter zone of the pnp transistor are simultaneously produced, by diffusion out from the structured first silicon layer. The first silicon layer is laterally insulated, and a second silicon layer is produced, doped with n-atoms, and structured with a mask. An emitter zone and a collector terminal zone of the npn transistor, a base terminal of the pnp transistor, and source and drain zones of an n-MOS transistor are simultaneously produced by diffusion out from the structured second silicon layer.

摘要翻译： 一种用于在同一半导体晶片上制造互补MOS晶体管和双极晶体管的方法，包括产生不同导电性的掩埋区，产生相应晶体管的n型和p型掺杂阱，并产生MOS晶体管的场氧化物区域和绝缘栅电极。 在制造场氧化物区域之后，利用用于产生npn晶体管的集电极区域和pnp的基极区域的第一掩模产生从半导体晶片的表面延伸到掩埋的n掺杂区域的高度掺杂的n区域 晶体管。 在制造绝缘栅电极之后，在整个表面上施加第一硅层并掺杂有p-原子。 辅助层在整个表面上施加在第一硅层上。 辅助层和第一硅层由第二掩模构成。 通过从结构化的第一硅层扩散，同时产生npn晶体管的基极接触区域，p-MOS晶体管的源极和漏极区域以及pnp晶体管的集电极区域和发射极区域。 第一硅层被横向绝缘，并且制造掺杂有n个原子并且用掩模构成的第二硅层。 npn晶体管的发射极区域和集电极端子区域，pnp晶体管的基极端子以及n-MOS晶体管的源极和漏极区域通过从结构化的第二硅层扩散而同时产生。