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    Memory systems and methods of operating the memory systems
    5.
    发明申请
    Memory systems and methods of operating the memory systems 有权
    内存系统和操作内存系统的方法

    公开(公告)号：US20080082762A1

    公开(公告)日：2008-04-03

    申请号：US11529711

    申请日：2006-09-28

    申请人： Andreas Taeuber ,  Detlev Richter ,  Luca de Ambroggi ,  Rainer Spielberg

    发明人： Andreas Taeuber ,  Detlev Richter ,  Luca de Ambroggi ,  Rainer Spielberg

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4239

    摘要： In one embodiment of the invention, a method of operating a memory system is provided, including concurrently reading data from a plurality of memories of the memory system and outputting the data from the memory system at an output channel capacity of an I/O port of the memory system by converting a data bus width of data read from at least some of the plurality of memories to a data bus width of the I/O port.

    摘要翻译： 在本发明的一个实施例中，提供了一种操作存储器系统的方法，包括同时从存储器系统的多个存储器读取数据，并以存储器系统的I / O端口的输出通道容量从存储器系统输出数据 所述存储器系统通过将从所述多个存储器中的至少一些存储器读取的数据的数据总线宽度转换为所述I / O端口的数据总线宽度。

    Integrated circuit with switching unit for memory cell coupling, and method for producing an integrated circuit for memory cell coupling
    6.
    发明授权
    Integrated circuit with switching unit for memory cell coupling, and method for producing an integrated circuit for memory cell coupling 有权
    具有用于存储单元耦合的开关单元的集成电路以及用于产生用于存储器单元耦合的集成电路的方法

    公开(公告)号：US07791940B2

    公开(公告)日：2010-09-07

    申请号：US12248505

    申请日：2008-10-09

    申请人： Andreas Taeuber

    发明人： Andreas Taeuber

    IPC分类号： G11C16/04

    CPC分类号： H01L27/105 ,  G11C5/063 ,  H01L27/0207

    摘要： An integrated circuit has a plurality of first memory cells, which are electrically coupled along a first line, and additionally has a plurality of second memory cells which are electrically coupled along a second line. The integrated circuit furthermore has a switching unit having a plurality of switching elements having in turn a first contact and a second contact. The first contact of a first switching element is coupled to the plurality of first memory cells, and the first contact of a second switching element is coupled to the plurality of second memory cells. In addition, the first contact of a third switching element is coupled to the second contact of the first switching element, and the first contact of a fourth switching element is coupled to the second contact of the second switching element.

    摘要翻译： 集成电路具有沿着第一线电耦合的多个第一存储器单元，并且还具有沿第二线电耦合的多个第二存储单元。 集成电路还具有开关单元，其具有多个开关元件，该多个开关元件又具有第一触点和第二触点。 第一开关元件的第一接触耦合到多个第一存储器单元，并且第二开关元件的第一接触耦合到多个第二存储器单元。 此外，第三开关元件的第一接触耦合到第一开关元件的第二触点，并且第四开关元件的第一触点耦合到第二开关元件的第二触点。

    DLL circuit for providing an output signal with a desired phase shift
    7.
    发明申请
    DLL circuit for providing an output signal with a desired phase shift 审中-公开
    DLL电路，用于提供具有所需相移的输出信号

    公开(公告)号：US20060197566A1

    公开(公告)日：2006-09-07

    申请号：US11358940

    申请日：2006-02-21

    申请人： Andreas Jakobs ,  Andreas Taeuber

    发明人： Andreas Jakobs ,  Andreas Taeuber

    IPC分类号： H03L7/06

    CPC分类号： H03K5/131

    摘要： The present invention relates to a DLL circuit for providing an output signal which is shifted with by a desired phase shift with respect to a periodic input signal. In one embodiment, the DLL Circuit comprises a plurality of delay elements all having the same delay time and being connected in series to form a delay chain, wherein the periodic input signal is applied to the first delay element of the delay chain. The DLL circuit further comprises a detection unit which is connected to the outputs of at least a portion of the delay elements and which is provided to determine which delay element a particular edge of the periodic signal has reached after a predetermined phase progress of the periodic signal, and to generate a corresponding control information which indicates at which delay element the particular edge of the periodic signal has last been determined. The DLL circuit further comprises a selection circuit for selecting one of the delay elements depending on the control information and depending on the desired phase shift and outputting the signal at the output of the selected delay elements as the output signal of the DLL circuit.

    摘要翻译： 本发明涉及一种用于提供输出信号的DLL电路，该输出信号相对于周期性输入信号被移位期望的相移。 在一个实施例中，DLL电路包括多个具有相同延迟时间并被串联连接以形成延迟链的延迟元件，其中周期性输入信号被施加到延迟链的第一延迟元件。 DLL电路还包括检测单元，其连接到延迟元件的至少一部分的输出，并且被提供用于确定在周期信号的预定相位进行之后周期信号的特定边缘已经到达的延迟元件 并且产生相应的控制信息，该控制信息指示周期信号的特定边缘最后被确定在哪个延迟元件。 DLL电路还包括一个选择电路，用于根据控制信息选择一个延迟元件，并根据期望的相移，并输出所选延迟元件的输出端的信号作为DLL电路的输出信号。

    Integrated Circuit with Switching Unit for Memory Cell Coupling, and Method for Producing an Integrated Circuit for Memory Cell Coupling
    8.
    发明申请
    Integrated Circuit with Switching Unit for Memory Cell Coupling, and Method for Producing an Integrated Circuit for Memory Cell Coupling 有权
    具有用于存储器单元耦合的开关单元的集成电路，以及用于产生用于存储器单元耦合的集成电路的方法

    公开(公告)号：US20090091976A1

    公开(公告)日：2009-04-09

    申请号：US12248505

    申请日：2008-10-09

    申请人： Andreas Taeuber

    发明人： Andreas Taeuber

    IPC分类号： G11C16/04 ,  G11C5/06 ,  H01L21/82

    CPC分类号： H01L27/105 ,  G11C5/063 ,  H01L27/0207

    摘要： An integrated circuit has a plurality of first memory cells, which are electrically coupled along a first line, and additionally has a plurality of second memory cells which are electrically coupled along a second line. The integrated circuit furthermore has a switching unit having a plurality of switching elements having in turn a first contact and a second contact. The first contact of a first switching element is coupled to the plurality of first memory cells, and the first contact of a second switching element is coupled to the plurality of second memory cells. In addition, the first contact of a third switching element is coupled to the second contact of the first switching element, and the first contact of a fourth switching element is coupled to the second contact of the second switching element.

    摘要翻译： 集成电路具有沿着第一线电耦合的多个第一存储器单元，并且还具有沿第二线电耦合的多个第二存储单元。 集成电路还具有开关单元，其具有多个开关元件，该多个开关元件又具有第一触点和第二触点。 第一开关元件的第一接触耦合到多个第一存储器单元，并且第二开关元件的第一接触耦合到多个第二存储器单元。 此外，第三开关元件的第一接触耦合到第一开关元件的第二触点，并且第四开关元件的第一触点耦合到第二开关元件的第二触点。

    Apparatus for generating memory-internal command signals from a memory operation command
    9.
    发明授权
    Apparatus for generating memory-internal command signals from a memory operation command 有权
    用于从存储器操作命令产生存储器内部命令信号的装置

    公开(公告)号：US06704243B2

    公开(公告)日：2004-03-09

    申请号：US10266187

    申请日：2002-10-07

    申请人： Rex Kho ,  Paul Schmoelz ,  Andreas Taeuber

    发明人： Rex Kho ,  Paul Schmoelz ,  Andreas Taeuber

    IPC分类号： G11C800

    CPC分类号： G11C7/109 ,  G11C7/1072 ,  G11C7/22

    摘要： A device for generating memory-internal command signals from a memory operation command includes a command input for receiving a memory operation command for performing a memory operation in a memory system, a clock signal input for receiving an external clock signal, and an output for applying the memory-internal command signal to a command signal line of the memory system. In the device, the memory-internal command signal is generated at a time which depends on the memory-internal command signal and which is selectively settable and synchronous with a rising or synchronous with a falling edge of the external clock signal.

    摘要翻译： 一种用于从存储器操作命令产生存储器内部命令信号的装置包括用于接收用于在存储器系统中执行存储器操作的存储器操作命令的命令输入，用于接收外部时钟信号的时钟信号输入和用于施加的输出 存储器内部命令信号发送到存储器系统的命令信号线。 在该装置中，存储器内部命令信号在取决于存储器内部命令信号的时刻产生，并且其被选择性地设置并且与外部时钟信号的下降沿同步。