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    High voltage vertical conduction superjunction semiconductor device
    6.
    再颁专利
    High voltage vertical conduction superjunction semiconductor device 有权
    高压垂直导通超导半导体器件

    公开(公告)号：USRE41509E1

    公开(公告)日：2010-08-17

    申请号：US11207203

    申请日：2005-08-18

    申请人： Daniel M. Kinzer ,  Srikant Sridevan

    发明人： Daniel M. Kinzer ,  Srikant Sridevan

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/405 ,  H01L29/408 ,  H01L29/41766

    摘要： A high voltage vertical conduction semiconductor device has a plurality of deep trenches or holes in a lightly doped body of one conductivity type. A diffusion of the other conductivity type is formed in the trench walls to a depth and a concentration which matches that of the body so that, under reverse blocking, both regions fully deplete. The elongated trench or hole is filled with a dielectric which may be a composite of nitride and oxide layers having a lateral dimension change matched to that of the silicon. The filler may also be a highly resistive SIPOS which permits leakage current flow from source to drain to ensure a uniform electric field distribution along the length of the trench during blocking.

    摘要翻译： 高电压垂直导电半导体器件在一种导电类型的轻掺杂体中具有多个深沟槽或孔。 在沟槽壁中形成另一导电类型的扩散，其深度和浓度与本体的深度和浓度相匹配，使得在反向封闭下，两个区域完全耗尽。 细长的沟槽或孔填充有电介质，其可以是具有与硅的侧向尺寸变化匹配的氮化物和氧化物层的复合材料。 填料还可以是高电阻性SIPOS，其允许泄漏电流从源极流到漏极，以确保在阻塞期间沿着沟槽的长度均匀的电场分布。

    III-Nitride power semiconductor device
    8.
    发明申请
    III-Nitride power semiconductor device 有权
    III型氮化物功率半导体器件

    公开(公告)号：US20080179631A1

    公开(公告)日：2008-07-31

    申请号：US11698371

    申请日：2007-01-26

    申请人： Daniel M. Kinzer

    发明人： Daniel M. Kinzer

    IPC分类号： H01L29/739

    CPC分类号： H01L29/2003 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/1029 ,  H01L29/7781 ,  H01L29/7786 ,  H01L29/7789

    摘要： An enhancement mode III-nitride power semiconductor device that includes normally-off channels along the sidewalls of a recess and a process for fabricating the same, the device including a first power electrode, a second power electrode, and a gate disposed between the first power electrode and the second power electrode over at least a sidewall of the recess.

    摘要翻译： 一种增强型III族氮化物功率半导体器件，其包括沿着凹部的侧壁的常态通道及其制造方法，该器件包括：第一电力电极，第二电力电极和设置在第一电力 电极，并且第二电源电极至少在凹部的侧壁上。

    Common MOSFET process for plural devices
    10.
    发明授权
    Common MOSFET process for plural devices 有权
    多个器件的常用MOSFET工艺

    公开(公告)号：US07273771B2

    公开(公告)日：2007-09-25

    申请号：US11054473

    申请日：2005-02-09

    申请人： Daniel M. Kinzer

    发明人： Daniel M. Kinzer

    IPC分类号： H01L21/332 ,  H01L21/00

    CPC分类号： H01L29/8725 ,  H01L27/0629 ,  H01L29/872

    摘要： A core process is described for the manufacture of a Schottky, MOSFET or Accufet, using a plurality of identical manufacturing steps, including spaced trenches, in a single production line, with the device type to be produced being defined at an implant and diffusion stage for forming very low concentration mesas for a Schottky; higher concentration mesas with source regions for Accufet devices and a channel implant and source implant for a vertical conduction MOSFET.

    摘要翻译： 描述了用于制造肖特基，MOSFET或Accufet的核心工艺，其在单个生产线中使用多个相同的制造步骤，包括间隔开的沟槽，待制造的器件类型被限定在植入和扩散阶段 形成肖特基非常低浓度的台面; 用于Accufet器件的源极区域的高浓度台面和用于垂直导通MOSFET的沟道注入和源极注入。