公开(公告)号：US5858826A

公开(公告)日：1999-01-12

申请号：US786052

申请日：1997-01-10

申请人： Chung-Yuan Lee ,  Chun-Yen Chang ,  Sun-Chieh Chien ,  Chen-Chiu Hsue

发明人： Chung-Yuan Lee ,  Chun-Yen Chang ,  Sun-Chieh Chien ,  Chen-Chiu Hsue

IPC分类号： H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823493

摘要： SRAMs conventionally formed on N-type substrates are instead formed on P-type substrates which have had the surface layer of the substrate converted to a blanket N-type well region. Preferably, the blanket N-type well region is formed by ion implantation of phosphorus ions to a dosage of between 5.times.10.sup.12 to 2.times.10.sup.13 /cm.sup.2 at an energy of 200-1000 KeV. Use of a P-type substrate having a blanket N-well region formed by ion implantation are less expensive than the N-type substrates conventionally used, and make the SRAM processing techniques compatible with the P-type substrates conventionally used in microprocessors and other logic devices.

摘要翻译： 通常形成在N型衬底上的SRAM替代地形成在已经将衬底的表面层转换为覆盖的N型阱区的P型衬底上。 优选地，在200-1000KV的能量下，通过将磷离子离子注入到5×10 12至2×10 13 / cm 2的剂量之间来形成覆盖的N型阱区。 使用具有通过离子注入形成的覆盖层N阱区域的P型衬底比常规使用的N型衬底便宜，并且使SRAM处理技术与常规用于微处理器和其它逻辑的P型衬底兼容 设备。

公开(公告)号：US5985709A

公开(公告)日：1999-11-16

申请号：US962116

申请日：1997-10-31

申请人： Chung-Yuan Lee ,  Chun-Yen Chang ,  Sun-Chieh Chien ,  Chen-Chiu Hsu

发明人： Chung-Yuan Lee ,  Chun-Yen Chang ,  Sun-Chieh Chien ,  Chen-Chiu Hsu

IPC分类号： H01L21/8238 ,  H01L21/8244 ,  H01L29/68

CPC分类号： H01L27/11 ,  H01L21/823892

摘要： A triple-well structure for semiconductor IC devices such as an SRAM IC device and a process for its fabrication, that allows for improved data storage stability as well as improved immunity capability against interference from device I/O bouncing and alpha particles. The triple-well structure includes at least one P-well in a P-type substrate, a number of N-wells, and a retrograde P-well formed within one of the N-wells. The process for fabricating the triple-well structure includes first implanting boron ions in the P-type substrate. A photomask is subsequently formed for the implantation of phosphorous ions in the region where a P-type MOS transistor is to be fabricated. A high temperature drive-in procedure is then employed to form a P-well and a number of N-wells. A selected area of one of the N-wells where an N-type MOS transistor is defined is then subjected to boron ion implantation, which is followed by an annealing procedure to form the retrograde P-well.

摘要翻译： 用于诸如SRAM IC器件的半导体IC器件的三阱结构及其制造方法，其允许改进的数据存储稳定性以及针对来自设备I / O弹跳和α粒子的干扰的改进的抗扰性能力。 三阱结构包括P型底物中的至少一个P阱，多个N阱和在N个孔内形成的逆行P阱。 制造三阱结构的工艺包括首先在P型衬底中注入硼离子。 随后形成用于在要制造P型MOS晶体管的区域中注入磷离子的光掩模。 然后采用高温驱动程序来形成P阱和多个N阱。 然后对定义有N型MOS晶体管的N阱中的一个选择区域进行硼离子注入，然后进行退火程序以形成逆行P阱。

公开(公告)号：US5541801A

公开(公告)日：1996-07-30

申请号：US450892

申请日：1995-05-26

申请人： Chung-Yuan Lee ,  Chun-Yen Chang

发明人： Chung-Yuan Lee ,  Chun-Yen Chang

IPC分类号： H01L27/02 ,  H03K17/0812 ,  H03K17/0814 ,  H02H9/04

CPC分类号： H01L27/0262 ,  H03K17/08128 ,  H03K17/08148

摘要： An electrostatic discharge (ESD) protection circuit for eliminating the stress of electrostatic discharge and preventing destruction of an internal semiconductor circuit. A first low-voltage gate trigger silicon controlled rectifier anode and anode gate, a second low-voltage gate trigger silicon controlled rectifier anode gate and a third low-voltage gate trigger silicon controlled rectifier anode gate are each coupled to a reference high potential. A second low-voltage gate trigger silicon controlled rectifier cathode and cathode gate and a third low-voltage gate trigger silicon controlled rectifier anode are each coupled to a reference low potential. A first low-voltage gate trigger silicon controlled rectifier cathode, a second low-voltage gate trigger silicon controlled rectifier anode and a third low-voltage gate trigger silicon controlled rectifier cathode are each coupled to a wire connected between a semiconductor pad and the semiconductor circuit. A current-limiting resistor is connected between the semiconductor pad and a linked terminal of trigger gates of the first low-voltage gate trigger silicon controlled rectifier, the second low-voltage gate trigger silicon controlled rectifier and the third low-voltage gate trigger silicon controlled rectifier.

摘要翻译： 一种用于消除静电放电应力并防止内部半导体电路破坏的静电放电（ESD）保护电路。 第一低电压栅极触发可控硅整流器阳极和阳极栅极，第二低压栅极触发器可控硅整流器阳极栅极和第三低压栅极触发器可控硅整流器阳极栅极分别耦合到参考高电位。 第二低电压栅极触发器可控硅整流器阴极和阴极栅极以及第三低压栅极触发器可控硅整流器阳极分别耦合到参考低电位。 第一低电压栅极触发器可控硅整流器阴极，第二低压栅极触发器可控硅整流器阳极和第三低压栅极触发器可控硅整流器阴极各自耦合到连接在半导体焊盘和半导体电路之间的导线 。 限流电阻器连接在半导体焊盘和第一低压栅极触发可控硅整流器的触发栅极的链接端子之间，第二低压栅极触发器可控硅整流器和第三低压栅极触发器被硅控制 整流器

公开(公告)号：US20170194098A1

公开(公告)日：2017-07-06

申请号：US15462954

申请日：2017-03-20

申请人： Chun-Yen Chang

发明人： Chun-Yen Chang

IPC分类号： H01G4/06 ,  H01G4/30 ,  H01G4/008

CPC分类号： H01G4/06 ,  H01G4/002 ,  H01G4/008 ,  H01G4/255 ,  H01G4/30

摘要： A magnetic capacitor includes a first electrode layer formed by depositing a first conducting material including graphene, a second electrode layer formed by depositing a second conducting material including graphene, and an insulator layer located between the first electrode layer and the second electrode layer. The magnetic capacitor further includes a first magnetized layer that includes one or more first ferro-magnetic elements that are magnetized to apply a first magnetic field to the insulator layer, and a second magnetized layer that includes one or more second ferro-magnetic elements that are magnetized to apply a second magnetic field to the insulator layer. The insulator layer is located between the first magnetized layer and the second magnetized layer. The first magnetic field and the second magnetic field improve a first electrical property of the magnetic capacitor.

公开(公告)号：US08148218B2

公开(公告)日：2012-04-03

申请号：US13044597

申请日：2011-03-10

申请人： Chun-Yen Chang

发明人： Chun-Yen Chang

IPC分类号： H01L21/335 ,  H01L21/336

CPC分类号： H01L29/0843 ,  H01L21/8258 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7783

摘要： The present invention is related to a semiconductor device with group III-V channel and group IV source-drain and a method for manufacturing the same. Particularly, the energy level density and doping concentration of group III-V materials are increased by the heteroepitaxy of group III-V and group IV materials and the structural design of elements. The method comprises: preparing a substrate; depositing a dummy gate material layer on the substrate and defining a dummy gate from the dummy gate material layer by photolithography; performing doping by self-aligned ion implantation using the dummy gate as a mask and performing activation at high temperature, so as to form source-drain; removing the dummy gate; forming a recess in the substrate between the source-drain pair by etching; forming a channel-containing stacked element in the recess by epitaxy; and forming a gate on the channel-containing stacked element.

摘要翻译： 本发明涉及具有III-V族通道和IV族源极漏极的半导体器件及其制造方法。 特别是Ⅲ-Ⅴ族材料的能级密度和掺杂浓度通过III-V族和IV族材料的异质外延和元素的结构设计增加。 该方法包括：制备基材; 在所述衬底上沉积虚拟栅极材料层并通过光刻从所述虚拟栅极材料层限定伪栅极; 使用伪栅极作为掩模通过自对准离子注入进行掺杂，并在高温下进行激活，以形成源极 - 漏极; 去除虚拟门; 通过蚀刻在源极 - 漏极对之间的衬底中形成凹陷; 通过外延在所述凹部中形成通道堆叠元件; 以及在含通道的堆叠元件上形成栅极。

公开(公告)号：US20090278165A1

公开(公告)日：2009-11-12

申请号：US12291396

申请日：2008-11-07

申请人： Chun-Yen Chang ,  Tsung Hsi Yang

发明人： Chun-Yen Chang ,  Tsung Hsi Yang

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L33/10 ,  H01L33/12 ,  H01L33/32

摘要： A light emitting device (LED) structure formed on a Group IV-based semiconductor substrate is provided. The LED structure includes a Group IV-based substrate, an AlN nucleation layer formed on the Group IV-based substrate, a GaN epitaxial layer formed on the AlN nucleation layer, a distributed Bragg reflector (DBR) multi-layer structure formed on the epitaxial layer, and an LED active layer formed on the DBR multi-layer structure.

摘要翻译： 提供了在基于IV族的半导体衬底上形成的发光器件（LED）结构。 LED结构包括基于IV族的衬底，在基于IV族的衬底上形成的AlN成核层，在AlN成核层上形成的GaN外延层，形成在外延层上的分布式布拉格反射器（DBR）多层结构 层和形成在DBR多层结构上的LED活性层。

公开(公告)号：US20090098714A1

公开(公告)日：2009-04-16

申请号：US12010242

申请日：2008-01-23

申请人： Chun-Yen Chang ,  Tsung-Hsi Yang ,  Shih-Guo Shen

发明人： Chun-Yen Chang ,  Tsung-Hsi Yang ,  Shih-Guo Shen

IPC分类号： H01L21/205

CPC分类号： H01L21/0265 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02639

摘要： GaN layer on semiconductor substrate is grown by using GaN nanorod buffer layer. Firstly, semiconductor substrate is cleaned and thermally degassed to remove the contaminant in the growth chamber. After the above step, the GaN nanorods layer is grown under the N-rich condition. Then, GaN epilayer is overgrown on the GaN nanorods layer under the Ga-rich condition for forming Group of III-Nitrides semiconductor layer on the semiconductor substrate.

摘要翻译： 通过使用GaN纳米棒缓冲层来生长半导体衬底上的GaN层。 首先，对半导体衬底进行清洁并热脱气以除去生长室中的污染物。 在上述步骤之后，在富氮条件下生长GaN纳米棒层。 然后，在半导体衬底上形成III族氮化物半导体层的Ga富集条件下，在GaN纳米棒层上过度生长GaN外延层。

公开(公告)号：US20070268724A1

公开(公告)日：2007-11-22

申请号：US11751072

申请日：2007-05-21

申请人： Chih-Liang Pan ,  Chun-Yen Chang ,  Han-Chang Cheng

发明人： Chih-Liang Pan ,  Chun-Yen Chang ,  Han-Chang Cheng

IPC分类号： F21V7/04

CPC分类号： G02F1/133611 ,  G02F1/133608 ,  G02F2001/133628

摘要： Disclosed are a backlight module and a liquid crystal display (LCD) including the same. The backlight module has a heat conductive structure so as to reduce the non-uniformity phenomenon of display. The backlight module comprises a frame, a reflective sheet, a heat-conductive plate, and a circuit board, wherein the frame has a bottom portion and at least one substantially step-typed through hole is formed therein. The reflective sheet is disposed on the inner surface of the bottom portion, and the heat-conductive plate is disposed in the step-typed through hole, and is spaced from the reflection sheet at a predetermined distance. The circuit board is disposed on the outer surface of the bottom portion of the frame, and has at least one electrical component that is received in the substantially step-typed through hole.

摘要翻译： 公开了一种背光模块和包括其的液晶显示器（LCD）。 背光模块具有导热结构，以减少显示的不均匀现象。 背光模块包括框架，反射片，导热板和电路板，其中框架具有底部，并且在其中形成至少一个基本上阶梯式的通孔。 反射片设置在底部的内表面上，并且导热板设置在台阶型通孔中，并且以预定距离与反射片隔开。 电路板设置在框架的底部的外表面上，并具有至少一个电气部件，该电气部件被容纳在大致阶梯型通孔中。

公开(公告)号：US20070134901A1

公开(公告)日：2007-06-14

申请号：US11652639

申请日：2007-01-12

申请人： Edward Chang ,  Guangli Luo ,  Tsung-Hsi Yang ,  Chun-Yen Chang

发明人： Edward Chang ,  Guangli Luo ,  Tsung-Hsi Yang ,  Chun-Yen Chang

IPC分类号： H01L21/28

CPC分类号： H01L21/0262 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02546 ,  H01L33/0066

摘要： This invention provides a process for growing Ge epitaixial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and subsequently growing a GaAs layer on Ge film of the surface of said Ge epitaixial layers by using metal organic chemical vapor deposition (MOCVD). The process comprises steps of, firstly, pre-cleaning a silicon wafer in a standard cleaning procedure, dipping it with HF solution and prebaking to remove its native oxide layer. Then, growing a high Ge-composition epitaixial layer, such as Si0.1Ge0.9 in a thickness of 0.8 μm on said Si substrate by using ultra-high vacuum chemical vapor deposition under certain conditions. Thus, many dislocations are generated and located near the interface and in the low of part of Si0.1Ge0.9 due to the large mismatch between this layer and Si substrate. Furthermore, a subsequent 0.8 μm Si0.05Ge0.95 layer, and/or optionally a further 0.8 μm Si0.02Ge0.98 layer, are grown. They form strained interfaces of said layers can bend and terminate the propagated upward dislocation very effectively. Therefore, a film of pure Ge is grown on the surface of said epitaixial layers. Finally, a GaAs epitaixial layer is grown on said Ge film by using MOCVD.

摘要翻译： 本发明提供了一种通过使用超高真空化学气相沉积（UHVCVD）在Si衬底上生长Ge表面层的方法，随后通过使用金属有机化学气相沉积在所述Ge附着层的表面的Ge膜上生长GaAs层 （MOCVD）。 该方法包括以下步骤：首先，在标准清洁程序中预清洁硅晶片，用HF溶液浸渍并预烘烤以除去其天然氧化物层。 然后，通过使用超高真空化学气相沉积在所述Si衬底上生长厚度为0.8μm的高Ge组成的表层，例如Si 0.1 O 0.1 Ge 0.9 在某些条件下 因此，由于该层和Si衬底之间的大的失配，产生许多位错并且位于界面附近和部分低Ge Ge 0.9的部分位置。 此外，随后的0.8μm的Si 0.05 Al 0.1 O 0.95层和/或任选的另外的0.8μm的Si 0.02 Co 0.98 < SUB>层，生长。 它们形成所述层的应变界面可以非常有效地弯曲和终止传播的向上错位。 因此，在所述附着层的表面上生长纯Ge的膜。 最后，通过使用MOCVD在所述Ge膜上生长GaAs外延层。

公开(公告)号：US20050233495A1

公开(公告)日：2005-10-20

申请号：US10859764

申请日：2004-06-03

申请人： Tsung-Hsi Yang ,  Chung-Liang Lee ,  Chu-Shou Yang ,  Guangli Luo ,  Wu-Ching Chou ,  Chun-Yen Chang ,  Tsung-Yeh Yang

发明人： Tsung-Hsi Yang ,  Chung-Liang Lee ,  Chu-Shou Yang ,  Guangli Luo ,  Wu-Ching Chou ,  Chun-Yen Chang ,  Tsung-Yeh Yang

IPC分类号： C30B23/08 ,  C23C14/06 ,  C23C16/30 ,  C30B23/02 ,  C30B29/48 ,  C30B29/52 ,  H01L21/00 ,  H01L21/06 ,  H01L21/10 ,  H01L21/203 ,  H01L21/205 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/365 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L31/0296 ,  C30B23/02 ,  C30B29/48 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0256 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/02631 ,  H01L33/0087

摘要： A technique to grow high quality and large area ZnSe layer on Si substrate is provided, comprising growing GexSi1-x/Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and finally growing a ZnSe film on top Ge buffer layers. Two concepts are applied in the process of this invention, the first one is to block the dislocations generated from GexSi1-x epitaxial layers and to terminate the propagated upward dislocations by using strained interfaces, accordingly the dislocation density of ZnSe layer is greatly reduced and the surface roughness is improved; the second concept is to solve the problems of anti-phase domain due to growth of polar materials on non-polar material using off-cut angle Si substrate, and that is free from diffusion problems between different atoms while generally growing ZnSe layers on Si substrate.

摘要翻译： 提供了在Si衬底上生长高质量和大面积ZnSe层的技术，其包括在Si衬底上生长Ge x Si x Si 1-x / Ge外延层， 高真空化学气相沉积（UHVCVD），最后在顶部Ge缓冲层上生长ZnSe膜。 在本发明的方法中应用了两个概念，第一个概念是为了阻止由Ge x 1 Si 1-x N外延层产生的位错并终止传播的向上位错 通过使用应变界面，ZnSe层的位错密度大大降低，表面粗糙度提高; 第二个概念是解决极性材料在非极性材料上使用偏角Si衬底生长的反相域问题，并且在不同原子之间没有扩散问题，而在Si衬底上通常生长ZnSe层 。