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    Method of making a blanket N-well structure for SRAM data stability in P-type substrates
    1.
    发明授权
    Method of making a blanket N-well structure for SRAM data stability in P-type substrates 失效
    在P型衬底中制作用于SRAM数据稳定性的覆盖N阱结构的方法

    公开(公告)号：US5858826A

    公开(公告)日：1999-01-12

    申请号：US786052

    申请日：1997-01-10

    申请人： Chung-Yuan Lee ,  Chun-Yen Chang ,  Sun-Chieh Chien ,  Chen-Chiu Hsue

    发明人： Chung-Yuan Lee ,  Chun-Yen Chang ,  Sun-Chieh Chien ,  Chen-Chiu Hsue

    IPC分类号： H01L21/8234 ,  H01L21/8238

    CPC分类号： H01L21/823493

    摘要： SRAMs conventionally formed on N-type substrates are instead formed on P-type substrates which have had the surface layer of the substrate converted to a blanket N-type well region. Preferably, the blanket N-type well region is formed by ion implantation of phosphorus ions to a dosage of between 5.times.10.sup.12 to 2.times.10.sup.13 /cm.sup.2 at an energy of 200-1000 KeV. Use of a P-type substrate having a blanket N-well region formed by ion implantation are less expensive than the N-type substrates conventionally used, and make the SRAM processing techniques compatible with the P-type substrates conventionally used in microprocessors and other logic devices.

    摘要翻译： 通常形成在N型衬底上的SRAM替代地形成在已经将衬底的表面层转换为覆盖的N型阱区的P型衬底上。 优选地，在200-1000KV的能量下，通过将磷离子离子注入到5×10 12至2×10 13 / cm 2的剂量之间来形成覆盖的N型阱区。 使用具有通过离子注入形成的覆盖层N阱区域的P型衬底比常规使用的N型衬底便宜，并且使SRAM处理技术与常规用于微处理器和其它逻辑的P型衬底兼容 设备。

    Multiple well device and process of manufacture
    2.
    发明授权
    Multiple well device and process of manufacture 失效
    多井设备和制造工艺

    公开(公告)号：US5698458A

    公开(公告)日：1997-12-16

    申请号：US680101

    申请日：1996-07-15

    申请人： Chen-Chiu Hsue ,  Sun-Chieh Chien ,  Chung-Yuan Lee ,  Ming-Tzong Yang

    发明人： Chen-Chiu Hsue ,  Sun-Chieh Chien ,  Chung-Yuan Lee ,  Ming-Tzong Yang

    IPC分类号： H01L21/8238 ,  H01L21/265

    CPC分类号： H01L21/823892

    摘要： A method of manufacture of a semiconductor device comprises forming a silicon dioxide film upon the surface of said device, forming patterns of silicon nitride upon the surface of said silicon dioxide film, ion implanting ions into said substrate adjacent to at least some of said silicon nitride patterns for well regions of a first polarity, forming a mask over said device, and deeply ion implanting with ions of opposite polarity into well regions of opposite polarity.

    摘要翻译： 一种制造半导体器件的方法包括在所述器件的表面上形成二氧化硅膜，在所述二氧化硅膜的表面上形成氮化硅图案，将离子注入所述衬底中，与所述氮化硅中的至少一些相邻 第一极性的阱区的图案，在所述器件上形成掩模，并且将具有相反极性的离子深入离子注入到相反极性的阱区中。

    Method for fabricating a local interconnection structure
    5.
    发明授权
    Method for fabricating a local interconnection structure 失效
    制造局部互连结构的方法

    公开(公告)号：US5750438A

    公开(公告)日：1998-05-12

    申请号：US658032

    申请日：1996-06-04

    申请人： Chen-Chiu Hsue ,  Sun-Chieh Chien

    发明人： Chen-Chiu Hsue ,  Sun-Chieh Chien

    IPC分类号： H01L21/768 ,  H01L21/283 ,  H01L21/306

    CPC分类号： H01L21/76889

    摘要： A local interconnection structure is disclosed. The local interconnection structure is formed on a silicon substrate in which a polysilicon gate and a number of diffusion regions exist. The structure includes a number of metal silicide layers over the substrate, a metal nitride layer over the silicide layers, and a dielectric layer over the nitride layer. The metal nitride layer which electrically connects the diffusion regions and the gate forms the interconnection. The method for fabricating the interconnection structure includes the steps of preparing the silicon substrate, sputtering a metal layer, annealing to form silicide and the nitride layers, depositing the dielectric layer, and patterning the nitride layer and the metal nitride by covering with a mask, etching away portions of both the dielectric layer and metal nitride layer not covered by the mask, and removing the mask after etching.

    摘要翻译： 公开了局部互连结构。 局部互连结构形成在其中存在多晶硅栅极和多个扩散区域的硅衬底上。 该结构包括在衬底上的多个金属硅化物层，在硅化物层之上的金属氮化物层，以及氮化物层上方的电介质层。 电连接扩散区域和栅极的金属氮化物层形成互连。 制造互连结构的方法包括以下步骤：制备硅衬底，溅射金属层，退火以形成硅化物和氮化物层，沉积电介质层，以及用掩模覆盖来对氮化物层和金属氮化物进行图案化， 蚀刻除了未被掩模覆盖的电介质层和金属氮化物层的部分，以及蚀刻后去除掩模。

    Method for forming a planar field oxide (fox) on substrates for integrated circuit
    6.
    发明授权
    Method for forming a planar field oxide (fox) on substrates for integrated circuit 失效
    在集成电路基板上形成平面场氧化物（fox）的方法

    公开(公告)号：US5554560A

    公开(公告)日：1996-09-10

    申请号：US315772

    申请日：1994-09-30

    申请人： Chen-Chiu Hsue ,  Sun-Chieh Chien ,  Ming-Hua Liu

    发明人： Chen-Chiu Hsue ,  Sun-Chieh Chien ,  Ming-Hua Liu

    IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76202 ,  H01L21/31055

    摘要： An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial leveling layer, such as spin-on-glass (SOG) or a anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The leveling layer is then etched back non-selectively by plasma etching to planarize the portion of the field oxide extending above the substrate surface. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages.

    摘要翻译： 实现了在硅衬底上制造平面场氧化物结构的改进方法。 该方法包括通过使用硅的LOCal氧化（LOCOS）工艺形成场氧化物，其中器件区域被氮化硅层防止氧化。 使用诸如旋涂玻璃（SOG）或抗反射涂层（ARC）层的牺牲调平层填充氮化硅和场氧化物结构之间的间隙，并使基板表面更平坦。 然后通过等离子体蚀刻非选择性地蚀刻流平层，以平坦化在衬底表面上方延伸的场氧化物的部分。 该方法不需要在硅衬底中蚀刻凹槽，因此具有一定的可靠性和成本优点。

    Process for fabrication of an SRAM cell having a highly doped storage node
    7.
    发明授权
    Process for fabrication of an SRAM cell having a highly doped storage node 失效
    具有高掺杂存储节点的SRAM单元的制造工艺

    公开(公告)号：US5472899A

    公开(公告)日：1995-12-05

    申请号：US216353

    申请日：1994-03-23

    申请人： Chen-Chiu Hsue ,  Sun-Chieh Chien

    发明人： Chen-Chiu Hsue ,  Sun-Chieh Chien

    IPC分类号： H01L21/8244 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/11

    摘要： An SRAM cell and a process for forming an SRAM cell comprises: forming a gate oxide layer on a semiconductor substrate, forming a gate on the gate oxide layer, forming a first ion implantation into the substrate in areas adjacent to the gate, performing a second ion implantation in an area immediately adjacent to the gate, depositing a dielectric layer over the gates, etching the dielectric layer to form a spacer structure therefrom, with the remainder of the dielectric layer being removed by the etching, and a third ion implantation in the substrate in all regions adjacent to the gates and the spacer forming more highly doped regions adjacent to the gate and the spacer.

    摘要翻译： SRAM单元和用于形成SRAM单元的工艺包括：在半导体衬底上形成栅极氧化层，在栅极氧化层上形成栅极，在与栅极相邻的区域中形成第一离子注入到衬底中，执行第二个 离子注入在与栅极紧邻的区域中，在栅极上沉积介电层，蚀刻电介质层以形成间隔结构，其中介电层的其余部分通过蚀刻去除，第三离子注入在 在与栅极相邻的所有区域中的衬底以及形成与栅极和间隔物相邻的更高掺杂区的衬垫。

    Process for forming a butting contact through a gate electrode
    8.
    发明授权
    Process for forming a butting contact through a gate electrode 失效
    用于通过栅电极形成对接接触的工艺

    公开(公告)号：US5521113A

    公开(公告)日：1996-05-28

    申请号：US405078

    申请日：1995-03-16

    申请人： Chen-Chiu Hsue ,  Sun-Chieh Chien

    发明人： Chen-Chiu Hsue ,  Sun-Chieh Chien

    IPC分类号： H01L27/11 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S148/02

    摘要： An SRAM cell includes a semiconductor substrate doped with a dopant of a first type, a highly doped region in the substrate implanted with a dopant of opposite type, a gate oxide layer on the substrate, a first conductive layer formed upon the gate oxide layer, a dielectric layer deposited over the first conductive layer, an opening in the gate oxide layer, the first conductive layer, and the dielectric layer, and a second conductive layer deposited upon the dielectric layer.

    摘要翻译： SRAM单元包括掺杂有第一类型的掺杂剂的半导体衬底，注入相反类型的掺杂剂的衬底中的高度掺杂区域，衬底上的栅极氧化物层，形成在栅极氧化物层上的第一导电层， 沉积在第一导电层上的电介质层，栅极氧化物层中的开口，第一导电层和介电层，以及沉积在电介质层上的第二导电层。

    Method of fabricating an asymmetric lightly doped drain transistor device
    9.
    发明授权
    Method of fabricating an asymmetric lightly doped drain transistor device 失效
    制造不对称轻掺杂漏极晶体管器件的方法

    公开(公告)号：US5510279A

    公开(公告)日：1996-04-23

    申请号：US369728

    申请日：1995-01-06

    申请人： Sun-Chieh Chien ,  Jengping Lin ,  Chen-Chiu Hsue

    发明人： Sun-Chieh Chien ,  Jengping Lin ,  Chen-Chiu Hsue

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8234

    CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7835 ,  H01L21/26586

    摘要： A method of fabricating an asymmetric lightly doped drain transistor device. The device's drain region is shielded with a barrier layer when ion implantation is applied to a implant a highly doped source region. A large angle implantation then follows to form a lightly doped pocket region adjacent to the highly doped source region. The implantation forming the pocket region increases the doping concentration along the device's source side which increases the device's threshold voltage diminishing short channel effects.

    摘要翻译： 一种制造不对称轻掺杂漏极晶体管器件的方法。 当离子注入施加到植入物高度掺杂的源区域时，器件的漏极区域被屏蔽层屏蔽。 然后，随后进行大角度注入以形成与高掺杂源区域相邻的轻掺杂袋区域。 形成口袋区域的注入增加了器件源极侧的掺杂浓度，这增加了器件的阈值电压降低了短沟道效应。

    Method of forming a capacitor
    10.
    发明授权
    Method of forming a capacitor 失效
    形成电容器的方法

    公开(公告)号：US5946571A

    公开(公告)日：1999-08-31

    申请号：US975495

    申请日：1997-11-21

    申请人： Chen-Chiu Hsue ,  Sun-Chieh Chien

    发明人： Chen-Chiu Hsue ,  Sun-Chieh Chien

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10852

    摘要： A DRAM capacitor is formed having a crown structure with a reduced number of processing steps. A planarized insulating layer is provided over the DRAM cell's transfer FET and a contact via is opened to one of the source/drain regions of the transfer FET. A layer of polysilicon is deposited to fill the contact via and to extend over the surface of the insulating layer, providing a thick polysilicon layer on the insulating layer. Conventional photolithography is used to define a first etching mask with an element on the thick polysilicon aligned over the contact via. The polysilicon layer is etched partially through using the first etching mask and the photoresist mask is removed. A layer of oxide is deposited over the elevated and recessed surfaces of the polysilicon layer and an etch back process is performed to form a second etching mask consisting of oxide spacer structures along the edges of the elevated portion of the polysilicon layer. Etching of the polysilicon layer is performed using the second etching mask, with the etch step proceeding completely through the recessed portions of the polysilicon layer and partially through the elevated portion of the polysilicon layer. The second etch mask is removed and a capacitor dielectric and an upper electrode are provided to complete formation of the charge storage capacitor for the DRAM cell.

    摘要翻译： 形成具有减少数量的处理步骤的表冠结构的DRAM电容器。 在DRAM单元的转移FET上提供平坦化的绝缘层，并且接触通孔对转移FET的源/漏区之一开放。 沉积多晶硅层以填充接触通孔并在绝缘层的表面上延伸，在绝缘层上提供厚的多晶硅层。 常规的光刻用于限定第一蚀刻掩模，其中厚多晶硅上的元件在接触通孔上对准。 通过使用第一蚀刻掩模部分蚀刻多晶硅层，并去除光致抗蚀剂掩模。 在多晶硅层的升高和凹陷表面上沉积一层氧化物，并且执行回蚀工艺以形成沿着多晶硅层的升高部分的边缘的氧化物间隔物结构构成的第二蚀刻掩模。 使用第二蚀刻掩模进行多晶硅层的蚀刻，蚀刻步骤完全通过多晶硅层的凹陷部分并部分地穿过多晶硅层的升高部分。 去除第二蚀刻掩模，并且提供电容器电介质和上电极以完成用于DRAM单元的电荷存储电容器的形成。