公开(公告)号：US5364812A

公开(公告)日：1994-11-15

申请号：US86524

申请日：1993-07-01

申请人： Masaaki Yashiro ,  Shigeki Morinaga ,  Clarence W. Teng

发明人： Masaaki Yashiro ,  Shigeki Morinaga ,  Clarence W. Teng

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10829 ,  Y10S257/90

摘要： The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area. A self-aligned process is used to form the source (14) and drain (12) for the pass gate transistor and automatic connection between the source of the transistor and the buried doping layer is made by the buried N+ layer. A sidewall silicon nitride passivation filament (38) is formed to protect the sidewalls of the interlevel insulator region between the first (30) and second (3-3, 3-4) polycrystalline silicon layers.

摘要翻译： 本发明的所描述的实施例提供了一种用于制造包括该单元的存储单元和存储器阵列的存储单元和方法。 存储单元是具有形成在基板（16）的主面的表面上的晶体管（1-1-2）的沟槽电容器型，并且在周围形成有基板的电容器（2-1-2） 的沟渠 电容器和晶体管通过与衬底具有相反导电类型的掩埋的重掺杂区域（26）连接。 具有与掩埋掺杂区相同的掺杂类型的掺杂存储区（24）围绕沟槽。 通过电介质层（32），在与沟槽区分开的沟槽中形成场板（30）。 场板延伸到存储单元之间的隔离区域，从而使用最小的表面积来提供电池之间的隔离。 自对准工艺用于形成栅极晶体管的源极（14）和漏极（12），晶体管的源极和掩埋掺杂层之间的自动连接由掩埋的N +层制成。 形成侧壁氮化硅钝化丝（38）以保护第一（30）和第二（3-3,3-4）多晶硅层之间的层间绝缘体区域的侧壁。

公开(公告)号：US5057887A

公开(公告)日：1991-10-15

申请号：US366801

申请日：1989-06-14

申请人： Masaaki Yashiro ,  Shigeki Morinaga ,  Clarence W. Teng

发明人： Masaaki Yashiro ,  Shigeki Morinaga ,  Clarence W. Teng

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/68 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L27/10829 ,  Y10S257/90

摘要： The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area. A self-aligned process is used to form the source (14) and drain (12) for the pass gate transistor and automatic connection between the source of the transistor and the buried doping layer is made by the buried N+ layer. A sidewall silicon nitride passivation filament (38) is formed to protect the sidewalls of the interlevel insulator region between the first (30) and second (3-3, 3-4) polycrystalline silicon layers.

公开(公告)号：US4958212A

公开(公告)日：1990-09-18

申请号：US292285

申请日：1988-12-30

申请人： Clarence W. Teng ,  William F. Richardson ,  Robert R. Doering ,  Ashwin H. Shah ,  Bing W. Shen ,  Mark Bordelon

发明人： Clarence W. Teng ,  William F. Richardson ,  Robert R. Doering ,  Ashwin H. Shah ,  Bing W. Shen ,  Mark Bordelon

IPC分类号： H01L27/108

CPC分类号： H01L27/10841

摘要： An improved memory cell layout (54) is formed including a trench cell (60) formed in a semiconductor substrate (58). The memory cell layout (54) includes a bitline (56) and a wordline (62) for storing and accessing charge. The charge is stored on a capacitor formed from a conductor (68), an insulating region (70) and a semiconductor substrate (58). Bitline (56) is primarily tangential to a trench cell (60), or may surround the periphery thereof. A wordline (62) overlies trench cell (60) and extends therein, and further may be formed of a width narrower than trench cell (60).

摘要翻译： 形成改进的存储单元布局（54），包括形成在半导体衬底（58）中的沟槽单元（60）。 存储单元布局（54）包括用于存储和访问电荷的位线（56）和字线（62）。 电荷存储在由导体（68），绝缘区（70）和半导体衬底（58）形成的电容器上。 位线（56）主要与沟槽单元（60）相切，或者可以围绕其周边。 字线（62）覆盖在沟槽单元（60）上并在其中延伸，并且还可以由窄于沟槽单元（60）的宽度形成。

公开(公告)号：US5671175A

公开(公告)日：1997-09-23

申请号：US670079

申请日：1996-06-26

申请人： Jiann Liu ,  Clarence W. Teng

发明人： Jiann Liu ,  Clarence W. Teng

IPC分类号： H01L27/108 ,  G11C11/24

CPC分类号： H01L27/10808 ,  Y10S257/908

摘要： A DRAM array (100) having reduced bitline capacitance. The DRAM cell includes a pass transistor and a storage capacitor (150). An isolation structure (108) surrounds the DRAM cell. The bitline (140) is connected to a source/drain region (120b) of the pass transistor using a first polysilicon plug (112). A second polysilicon plug (110) connects the storage capacitor (150) to the other source/drain region (120a&c) of the pass transistor. Both polysilicon plugs (110, 112) extend through an interlevel dielectric layer (116) to one of the source/drain region (120a-c) of the pass transistor, but neither extends over the isolation structure (108). If desired, either the storage capacitor (150) or the bitline (140) may be offset from the source/drain regions (120a-c).

摘要翻译： 具有降低的位线电容的DRAM阵列（100）。 DRAM单元包括传输晶体管和存储电容器（150）。 隔离结构（108）围绕DRAM单元。 位线（140）使用第一多晶硅插头（112）连接到传输晶体管的源极/漏极区域（120b）。 第二多晶硅插头（110）将存储电容器（150）连接到传输晶体管的另一个源极/漏极区域（120a和c）。 两个多晶硅插头（110,112）延伸穿过层间电介质层（116）到通过晶体管的源极/漏极区域（120a-c）之一，但是两者都不延伸到隔离结构（108）上。 如果需要，存储电容器（150）或位线（140）可能偏离源极/漏极区域（120a-c）。

公开(公告)号：US5595925A

公开(公告)日：1997-01-21

申请号：US236745

申请日：1994-04-29

申请人： Ih-Chin Chen ,  Hisashi Shichijo ,  Clarence W. Teng

发明人： Ih-Chin Chen ,  Hisashi Shichijo ,  Clarence W. Teng

IPC分类号： H01L21/8238 ,  H01L21/8226 ,  H01L21/8242 ,  H01L27/082 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10805 ,  H01L27/105

摘要： A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n-type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

摘要翻译： 动态随机存取存储器件（10）包括三个单独的部分 - 输入/输出部分（12），外围晶体管部分（14）和存储器阵列部分（16），全部形成在p型衬底层 18）。 动态随机存取存储器件（10）可以为每个部分采用单独的衬底偏置电压。 输入/输出部分（12）具有通过n型阱区域（20）与p-型衬底层（18）隔离的p-型区域（22）。 外围晶体管部分（14）具有p型区域（36），其可以通过可选的n型阱区域（40）与p型衬底层（18）隔离，用于那些需要不同衬底偏置的器件 外围晶体管部分（14）和存储器阵列部分（16）之间的电压。

公开(公告)号：US5087591A

公开(公告)日：1992-02-11

申请号：US169078

申请日：1988-03-16

申请人： Clarence W. Teng

发明人： Clarence W. Teng

IPC分类号： H01L21/311 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/31116

摘要： Contact etching is simplified by including a conformal etch stop layer underneath the interlevel or multilevel oxide (MLO). Etching through the unequal thickness of the MLO with sufficient overetching to reliably clear the thickest parts of the MLO layer will therefore not damage the silicon contact areas underneath the thinner parts of the MLO. Process control is also improved.Preferably this conformal etch stop layer is a conductor, and is grounded to configure a field plate over the entire surface of the chip.

摘要翻译： 通过在层间或多层氧化物（MLO）下方包括保形蚀刻停止层来简化接触蚀刻。 因此，通过足够的过蚀刻使MLO的不均匀厚度蚀刻以可靠地清除MLO层的最厚部分，因此不会损坏MLO较薄部分下方的硅接触区域。 过程控制也得到改善。 优选地，该保形蚀刻停止层是导体，并且被接地以在芯片的整个表面上配置场板。

公开(公告)号：US5049519A

公开(公告)日：1991-09-17

申请号：US426258

申请日：1989-10-25

申请人： Clarence W. Teng

发明人： Clarence W. Teng

IPC分类号： H01L27/092

CPC分类号： H01L27/0921

摘要： A latch-up free CMOS structure and method of fabrication thereof is disclosed. A P-type substrate (40) is appropriately masked to form a plurality of sites in which isolated wells (50) are formed. A thermal oxide layer (56) is grown on the surface of each well (50), and a boron channel stop (62) implanted therearound. Polysilicon semiconductor material (68) is formed within each well, and implant doped to form an N-well (76) of material. The P-substrate (40) is planarized. PMOS transistors are formed within the oxide isolate N-wells (76), while NMOS transistors are formed in the P-substrate (40) outside the wells.

摘要翻译： 公开了一种无闩锁CMOS结构及其制造方法。 适当地掩蔽P型衬底（40）以形成其中形成隔离阱（50）的多个位置。 在每个孔（50）的表面上生长热氧化物层（56），并且在其周围植入硼通道停止件（62）。 在每个阱内形成多晶硅半导体材料（68），并且掺杂掺杂以形成材料的N阱（76）。 P基板（40）被平坦化。 PMOS晶体管形成在氧化物隔离N阱（76）内，而NMOS晶体管形成在阱外部的P衬底（40）中。

公开(公告)号：US5043778A

公开(公告)日：1991-08-27

申请号：US238978

申请日：1988-08-25

申请人： Clarence W. Teng ,  Thomas E. Tang ,  Che-Chia Wei

发明人： Clarence W. Teng ,  Thomas E. Tang ,  Che-Chia Wei

IPC分类号： H01L21/285 ,  H01L21/308 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/66636 ,  H01L21/28525 ,  H01L21/3086 ,  H01L21/76218 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0847 ,  H01L27/0921 ,  H01L27/0928 ,  Y10S257/90

摘要： A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 formed by using a silicon etch to form a recess, limiting the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusioins 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

摘要翻译： 具有源极/漏极 - 接触区域36的MOS体器件，其几乎完全由电介质35隔离。这些通过使用硅蚀刻形成凹槽形成的“源极/漏极”区域36，用氧化物限制蚀刻的凹槽，并且填充 与多晶硅。 短的各向同性氧化物蚀刻，随后是多晶硅长丝沉积，然后在氧化物隔离的源极/漏极 - 接触区域36和有源器件的沟道区域33之间接触。 通过该接触的小面积的扩散将在硅中形成小的漫射体44，其作为电学有效的源极/漏极区域。 在栅极上使用侧壁氮化物细丝30允许硅蚀刻步骤自对准。

公开(公告)号：US4656732A

公开(公告)日：1987-04-14

申请号：US654998

申请日：1984-09-26

申请人： Clarence W. Teng ,  Roger A. Haken

发明人： Clarence W. Teng ,  Roger A. Haken

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/283

CPC分类号： H01L21/76802

摘要： Integrated circuits wherein the width of contacts is narrowed by a sidewall oxide, so that the metal layer can be patterned to minimum geometry everywhere, and does not have to be widened where it runs over a contact.

摘要翻译： 集成电路，其中触点的宽度被侧壁氧化物变窄，使得金属层可以被图案化到任何地方的最小几何形状，并且不必在其在触点上运行的地方加宽。

公开(公告)号：US5587614A

公开(公告)日：1996-12-24

申请号：US473807

申请日：1995-06-07

申请人： Chorng-Lii Hwang ,  Clarence W. Teng

发明人： Chorng-Lii Hwang ,  Clarence W. Teng

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L27/02 ,  H01L27/00

CPC分类号： H01L28/40 ,  H01L21/7684

摘要： A method of improving the dielectric properties of a thin dielectric disposed on a polycrystalline material, a method of forming a capacitor therewith and the capacitor. An electrode (17) having a polycrystalline material surface having voids (23) extending to the surface, preferably silicon, is provided. A layer of an amorphous form of the material (19) having a thickness of from about 20 .ANG. to about 500 .ANG. is formed over the surface with the amorphous layer disposed within the voids. A thin layer of a dielectric (21) is formed over the amorphous layer and, in the fabrication of a capacitor, a layer of electrical conductor (25) is provided which is spaced from the material over the dielectric. A microcontaminant can be disposed between the polycrystalline material surface and the amorphous layer.

摘要翻译： 一种改善设置在多晶材料上的薄电介质的介电性能的方法，与其形成电容器的方法和电容器。 提供具有多晶材料表面的电极（17），其具有延伸到表面的空隙（23），优选为硅。 在表面上形成厚度为约20埃至约500埃的材料（19）的无定形形式的层，其中非晶层设置在空隙内。 电介质（21）的薄层形成在非晶层之上，并且在电容器的制造中，提供与电介质上的材料间隔开的电导体层（25）。 微量微粒可以设置在多晶材料表面和非晶层之间。