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    High performance direct coupled FET memory cell
    1.
    发明授权
    High performance direct coupled FET memory cell 失效
    高性能直接耦合FET存储单元

    公开(公告)号：US6137129A

    公开(公告)日：2000-10-24

    申请号：US2825

    申请日：1998-01-05

    申请人： Claude L. Bertin ,  John E. Cronin ,  Erik L. Hedberg ,  Jack A. Mandelman

    发明人： Claude L. Bertin ,  John E. Cronin ,  Erik L. Hedberg ,  Jack A. Mandelman

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L27/108 ,  H01L29/74 ,  H01L29/76

    CPC分类号： H01L27/11 ,  Y10S257/903

    摘要： A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETS, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO.sub.2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer. Second, the cell pass gates are formed on a pass gate or Input/Output (I/O) layer. Third, the I/O layer is bonded to and connected to the preferred latch layer.

    摘要翻译： 一对直接耦合的场效应晶体管（FET），直接耦合FETS的锁存器，包括直接耦合FET的锁存器的静态随机存取存储器（SRAM）单元和形成直接耦合的FET结构的过程，锁存器和SRAM单元 。 可以是PFET，NFET或者其中之一的垂直FET是由栅极氧化物SiO 2分离的外延生长的NPN或PNP堆叠。 每个设备的门是该对的另一个设备的源或漏极。 优选实施例锁存器包括两对这样的直接耦合的垂直FET对，连接在一起以形成交叉耦合的反相器。 通路栅极层结合到优选实施例锁存器的一个表面上以形成优选实施例SRAM单元的阵列。 SRAM单元可以包括一个或两个传递门。 优选实施例SRAM过程具有三个主要步骤。 首先，优选实施例的锁存器形成在硅晶片上的氧化物层中。 第二，在传输门或输入/输出（I / O）层上形成单元传输门。 第三，I / O层被粘合并连接到优选的锁存层。

    High performance direct coupled FET memory cell
    2.
    发明授权
    High performance direct coupled FET memory cell 失效
    高性能直接耦合FET存储单元

    公开(公告)号：US06426530B1

    公开(公告)日：2002-07-30

    申请号：US09568663

    申请日：2000-05-10

    申请人： Claude L. Bertin ,  John E. Cronin ,  Erik L. Hedberg ,  Jack A. Mandelman

    发明人： Claude L. Bertin ,  John E. Cronin ,  Erik L. Hedberg ,  Jack A. Mandelman

    IPC分类号： H01L2976

    CPC分类号： H01L27/11 ,  Y10S257/903

    摘要： A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETs, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer. Second, the cell pass gates are formed on a pass gate or Input/Output (I/O) layer. Third, the I/O layer is bonded to and connected to the preferred latch layer.

    摘要翻译： 一对直接耦合的场效应晶体管（FET），直接耦合的FET的锁存器，包括直接耦合的FET的锁存器的静态随机存取存储器（SRAM）单元和形成直接耦合的FET结构的过程，锁存器和SRAM单元 。 可以是PFET，NFET或者其中之一的垂直FET是由栅极氧化物SiO 2分离的外延生长的NPN或PNP堆叠。 每个设备的门是该对的另一个设备的源或漏极。 优选实施例锁存器包括两对这样的直接耦合的垂直FET对，连接在一起以形成交叉耦合的反相器。 通路栅极层结合到优选实施例锁存器的一个表面上以形成优选实施例SRAM单元的阵列。 SRAM单元可以包括一个或两个传递门。 优选实施例SRAM过程具有三个主要步骤。 首先，优选实施例的锁存器形成在硅晶片上的氧化物层中。 第二，在传输门或输入/输出（I / O）层上形成单元传输门。 第三，I / O层被粘合并连接到优选的锁存层。

    Shadow ram cell having a shallow trench eeprom
    7.
    发明授权
    Shadow ram cell having a shallow trench eeprom 失效
    阴影柱塞细胞具有浅沟eeprom

    公开(公告)号：US5196722A

    公开(公告)日：1993-03-23

    申请号：US848913

    申请日：1992-03-12

    申请人： Albert S. Bergendahl ,  Claude L. Bertin ,  John E. Cronin ,  Howard L. Kalter ,  Donald M. Kenney ,  Chung H. Lam ,  Hsing-San Lee

    发明人： Albert S. Bergendahl ,  Claude L. Bertin ,  John E. Cronin ,  Howard L. Kalter ,  Donald M. Kenney ,  Chung H. Lam ,  Hsing-San Lee

    IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L29/788

    CPC分类号： H01L27/10829 ,  H01L27/105 ,  H01L29/7881

    摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.

    摘要翻译： 公开了一种形成在半导体衬底上的半导体器件存储器阵列，其包括设置成阵列的多个场效应晶体管DRAM器件。 每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM-EEPROM对共享共同的漏极扩散。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极和连续的水平布置的程序和调用栅极多晶硅电极。 浮动栅极与程序分离，并通过富含硅的氮化物来调用栅极。 本发明的阵列提供高密度影子RAM。 还公开了用于制造本发明的装置的方法。