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    High performance direct coupled FET memory cell
    1.
    发明授权
    High performance direct coupled FET memory cell 失效
    高性能直接耦合FET存储单元

    公开(公告)号：US6137129A

    公开(公告)日：2000-10-24

    申请号：US2825

    申请日：1998-01-05

    申请人： Claude L. Bertin ,  John E. Cronin ,  Erik L. Hedberg ,  Jack A. Mandelman

    发明人： Claude L. Bertin ,  John E. Cronin ,  Erik L. Hedberg ,  Jack A. Mandelman

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L27/108 ,  H01L29/74 ,  H01L29/76

    CPC分类号： H01L27/11 ,  Y10S257/903

    摘要： A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETS, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO.sub.2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer. Second, the cell pass gates are formed on a pass gate or Input/Output (I/O) layer. Third, the I/O layer is bonded to and connected to the preferred latch layer.

    摘要翻译： 一对直接耦合的场效应晶体管（FET），直接耦合FETS的锁存器，包括直接耦合FET的锁存器的静态随机存取存储器（SRAM）单元和形成直接耦合的FET结构的过程，锁存器和SRAM单元 。 可以是PFET，NFET或者其中之一的垂直FET是由栅极氧化物SiO 2分离的外延生长的NPN或PNP堆叠。 每个设备的门是该对的另一个设备的源或漏极。 优选实施例锁存器包括两对这样的直接耦合的垂直FET对，连接在一起以形成交叉耦合的反相器。 通路栅极层结合到优选实施例锁存器的一个表面上以形成优选实施例SRAM单元的阵列。 SRAM单元可以包括一个或两个传递门。 优选实施例SRAM过程具有三个主要步骤。 首先，优选实施例的锁存器形成在硅晶片上的氧化物层中。 第二，在传输门或输入/输出（I / O）层上形成单元传输门。 第三，I / O层被粘合并连接到优选的锁存层。

    High performance direct coupled FET memory cell
    2.
    发明授权
    High performance direct coupled FET memory cell 失效
    高性能直接耦合FET存储单元

    公开(公告)号：US06426530B1

    公开(公告)日：2002-07-30

    申请号：US09568663

    申请日：2000-05-10

    申请人： Claude L. Bertin ,  John E. Cronin ,  Erik L. Hedberg ,  Jack A. Mandelman

    发明人： Claude L. Bertin ,  John E. Cronin ,  Erik L. Hedberg ,  Jack A. Mandelman

    IPC分类号： H01L2976

    CPC分类号： H01L27/11 ,  Y10S257/903

    摘要： A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETs, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer. Second, the cell pass gates are formed on a pass gate or Input/Output (I/O) layer. Third, the I/O layer is bonded to and connected to the preferred latch layer.

    摘要翻译： 一对直接耦合的场效应晶体管（FET），直接耦合的FET的锁存器，包括直接耦合的FET的锁存器的静态随机存取存储器（SRAM）单元和形成直接耦合的FET结构的过程，锁存器和SRAM单元 。 可以是PFET，NFET或者其中之一的垂直FET是由栅极氧化物SiO 2分离的外延生长的NPN或PNP堆叠。 每个设备的门是该对的另一个设备的源或漏极。 优选实施例锁存器包括两对这样的直接耦合的垂直FET对，连接在一起以形成交叉耦合的反相器。 通路栅极层结合到优选实施例锁存器的一个表面上以形成优选实施例SRAM单元的阵列。 SRAM单元可以包括一个或两个传递门。 优选实施例SRAM过程具有三个主要步骤。 首先，优选实施例的锁存器形成在硅晶片上的氧化物层中。 第二，在传输门或输入/输出（I / O）层上形成单元传输门。 第三，I / O层被粘合并连接到优选的锁存层。

    High performance, low power vertical integrated CMOS devices
    3.
    发明授权
    High performance, low power vertical integrated CMOS devices 失效

    公开(公告)号：US06518112B2

    公开(公告)日：2003-02-11

    申请号：US09899262

    申请日：2001-07-06

    申请人： Michael D. Armacost ,  Claude L. Bertin ,  Erik L. Hedberg ,  Jack A. Mandelman

    发明人： Michael D. Armacost ,  Claude L. Bertin ,  Erik L. Hedberg ,  Jack A. Mandelman

    IPC分类号： H01L31119

    CPC分类号： H01L27/11 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203 ,  Y10S257/903

    摘要： A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETs; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the device's channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e.g., PNPNP or NPNPN, each with its own gate, i.e., the side of a polysilicon gate layer. The SRAM cell may be radiation hardened by selectively thickening gate layers to increase storage node capacitance, providing high resistance cell wiring or by including a multi-layered gate oxide layer of NO or ONO, or by any combination thereof.

    High performance, low power vertical integrated CMOS devices
    5.
    发明授权
    High performance, low power vertical integrated CMOS devices 失效
    高性能，低功耗的垂直集成CMOS器件

    公开(公告)号：US06297531B2

    公开(公告)日：2001-10-02

    申请号：US09002399

    申请日：1998-01-05

    申请人： Michael D. Armacost ,  Claude L. Bertin ,  Erik L. Hedberg ,  Jack A. Mandelman

    发明人： Michael D. Armacost ,  Claude L. Bertin ,  Erik L. Hedberg ,  Jack A. Mandelman

    IPC分类号： H01L2976

    CPC分类号： H01L27/11 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203 ,  Y10S257/903

    摘要： A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETS; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the device's channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e.g., PNPNP or NPNPN, each with its own gate, i.e., the side of a polysilicon gate layer. The SRAM cell may be radiation hardened by selectively thickening gate layers to increase storage node capacitance, providing high resistance cell wiring or by including a multi-layered gate oxide layer of NO or ONO, or by any combination thereof.

    摘要翻译： 可以是N型FET（NFET）或P型FET（PFET）的垂直场效应晶体管（FET）; 可以是两个或更多个NFET或两个或更多个PFETS的多器件垂直结构; 逻辑门包括至少一个垂直FET或至少一个多器件垂直; 包括至少一个垂直FET的静态随机存取存储器（SRAM）单元和阵列; 包括至少一个这样的SRAM单元的存储器阵列; 以及形成垂直FET结构的过程，垂直多器件（multi-FET）结构，逻辑门和SRAM单元。 垂直FET是NPN或PNP的外延生长层叠堆叠，其中多晶硅栅极层的侧面与器件的沟道层相邻。 多FET结构可以通过形成与相同沟道层相邻的两个或多个栅极的侧面，或者通过在相同的堆叠中形成多个通道层，例如PNPNP或NPNPN，每个具有其自己的栅极，即侧面 的多晶硅栅极层。 SRAM单元可以通过选择性地增厚栅极层而辐射硬化，以增加存储节点电容，提供高电阻电池布线或者通过包括NO或ONO的多层栅极氧化物层或其任何组合。

    Programmable latch device with integrated programmable element
    6.
    发明授权
    Programmable latch device with integrated programmable element 有权
    具有集成可编程元件的可编程锁存器件

    公开(公告)号：US06420925B1

    公开(公告)日：2002-07-16

    申请号：US09757267

    申请日：2001-01-09

    申请人： John A. Fifield ,  Erik L. Hedberg ,  Claude L. Bertin ,  Nicholas M. van Heel

    发明人： John A. Fifield ,  Erik L. Hedberg ,  Claude L. Bertin ,  Nicholas M. van Heel

    IPC分类号： H01H3776

    CPC分类号： H03K3/356008 ,  G11C17/18

    摘要： According to the present invention, a programable latch device for use in personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment programmable latch device can use both fuses and antifuses as programmable elements. The programmable latch device provides a solid digital output indicative of the state of the programmable device, and can be reliably read to provide customization and personalization of associated semiconductor devices. The preferred embodiment programable latch device includes an integrated fuse or antifuse as a programmable element in the latch device. By integrating the programmable element into the latch, device size and complexity is minimized. In particular, the number of transistors required drops considerably when compared to prior art approaches.

    摘要翻译： 根据本发明，提供了用于个性化半导体器件的可编程锁存器件，其克服了现有技术的限制。 优选实施例可编程锁存器件可以使用熔丝和反熔丝作为可编程元件。 可编程锁存器件提供指示可编程器件状态的实心数字输出，并且可被可靠地读取以提供相关半导体器件的定制和个性化。 优选实施例可编程锁存装置包括作为锁存装置中的可编程元件的集成熔丝或反熔丝。 通过将可编程元件集成到锁存器中，器件尺寸和复杂度最小化。 特别地，与现有技术方法相比，所需的晶体管的数量显着下降。

    Structures for wafer level test and burn-in
    7.
    发明授权
    Structures for wafer level test and burn-in 失效
    晶圆级测试和老化的结构

    公开(公告)号：US06233184B1

    公开(公告)日：2001-05-15

    申请号：US09191954

    申请日：1998-11-13

    申请人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    发明人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    IPC分类号： G11C2900

    CPC分类号： G01R31/2855 ,  G01R31/2806 ,  G01R31/2831 ,  G01R31/31905 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014

    摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.

    摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

    High frequency valid data strobe
    8.
    发明授权
    High frequency valid data strobe 失效
    高频有效数据选通

    公开(公告)号：US06177807B1

    公开(公告)日：2001-01-23

    申请号：US09322465

    申请日：1999-05-28

    申请人： Claude L. Bertin ,  John A. Fifield ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

    发明人： Claude L. Bertin ,  John A. Fifield ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

    IPC分类号： G03K1716

    CPC分类号： G06F13/4086 ,  H03K5/06 ,  H04L25/0298

    摘要： A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.

    摘要翻译： 具有存储器发送/接收控制电路的处理器，包括总线驱动电路和经由控制总线连接到存储器的控制输入端的检测器电路。 数据输入线或输出线或数据输入/输出线连接在处理器和存储器之间。 具有递增可变长度的传输线短截线连接到控制线14的存储器控​​制输入侧。传输线短截线的阻抗Z0等于控制线的阻抗Z0，并在结束时开路 在电压倍增以实现控制信号和数据信号之间的高速同步，并确保在高时钟速率下的有效数据。

    Reconfigurable I/O DRAM
    9.
    发明授权
    Reconfigurable I/O DRAM 失效
    可重配置I / O DRAM

    公开(公告)号：US6070262A

    公开(公告)日：2000-05-30

    申请号：US833367

    申请日：1997-04-04

    申请人： Mark W. Kellogg ,  Timothy J. Dell ,  Erik L. Hedberg ,  Claude L. Bertin

    发明人： Mark W. Kellogg ,  Timothy J. Dell ,  Erik L. Hedberg ,  Claude L. Bertin

    IPC分类号： G06F11/10 ,  G06F12/00 ,  G11C7/10 ,  G11C29/00

    CPC分类号： G11C7/1057 ,  G06F11/1044 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084

    摘要： A Dynamic Random Access Memory (DRAM) configurable by eight (.times.8) or by nine (.times.9). The DRAM has nine Data Input/Outputs (I/Os). The memory array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is configured .times.8, one I/O is held in its high impedance state; one ninth of the DRAM's data path (between the array and the ninth I/O) is ignored; and, the entire array address space is available for data storage through eight I/Os. When the DRAM is configured .times.9, all nine I/Os are active; the DRAM I/O path is reconfigured with part of the array providing the ninth bit through the ninth I/O; and the array address space reduced by one-eighth. All nine bits may be from a common sub-array. Alternatively, sub-arrays may be paired so that when the DRAM is configured .times.9, eight bits are accessed in seven-eighths of one sub-array, with the ninth bit being accessed in one eighth of the other sub-array of the pair.

    摘要翻译： 动态随机存取存储器（DRAM）可由八（x8）或九（x9）配置。 DRAM具有9个数据输入/输出（I / O）。 存储器阵列被分成两个或更多个子阵列，子阵列单元被布置成可寻址的行和列。 当DRAM被配置为x8时，一个I / O保持在其高阻抗状态; DRAM的数据路径（阵列和第九个I / O之间）的九分之一被忽略; 并且整个阵列地址空间可用于通过八个I / O进行数据存储。 当DRAM配置为x9时，所有9个I / O都有效; DRAM I / O路径被配置为通过第九个I / O提供第九位的阵列的一部分; 并且阵列地址空间减少了八分之一。 所有9位可能来自公共子阵列。 或者，子阵列可以配对，使得当DRAM被配置为x9时，在一个子阵列的七分之八中访问八个比特，其中第九比特在该对的另一个子阵列的八分之一中被访问。