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1.发明授权Refractory metal capacitor structures, particularly for analog integrated circuit devices 失效耐火金属电容器结构，特别适用于模拟集成电路器件
公开(公告)号：US4638400A
公开(公告)日：1987-01-20
申请号：US790911
申请日：1985-10-24
IPC分类号： H01L27/04 , H01G4/12 , H01G4/33 , H01G4/40 , H01L21/822 , H01L29/92 , H01G1/015 , B41M3/08 , H01L27/02
CPC分类号： H01L28/40
摘要： A capacitor structure which is particularly suitable for use in analog integrated circuit devices employs an intermediate layer of a refractory metal disposed in a thin layer overlying a flat dielectric surface. The thinness and the low reflectivity of the refractory metal facilitates precise patterning of the upper plate of the capacitor structure. In the present invention, capacitance is no longer determined by imprecise cuts through thick oxide layers or by patterning of thick metallization layers within these apertures. The use of refractory metals in the capacitor structure also readily permits the incorporation of resistive circuit elements.
摘要翻译： 特别适用于模拟集成电路器件的电容器结构使用设置在覆盖在平坦电介质表面上的薄层中的难熔金属的中间层。 难熔金属的薄度和低反射率有助于电容器结构的上板的精确图案化。 在本发明中，电容不再通过不精确的切割穿过厚的氧化物层或通过在这些孔内图案化厚的金属化层来确定。 在电容器结构中使用难熔金属也容易地并入电阻电路元件。
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公开(公告)号：US4146904A
公开(公告)日：1979-03-27
申请号：US861673
申请日：1977-12-19
IPC分类号： G01T1/24 , G01T1/20 , H01L31/0232 , H01L31/09 , H01L31/10 , H01L31/103 , H01L27/14 , G01T1/22
CPC分类号： H01L31/02322 , G01T1/2018 , H01L31/103
摘要： In a substrate of semiconductor material of one conductivity type and high resistivity, a thin layer of the same conductivity and low resistivity is provided adjacent a major surface of the substrate. A region of opposite conductivity type is provided in the substrate adjacent the major surface to form a PN junction therewith spaced adjacent to the thin layer. Zero bias is provided on the PN junction. Minority charge carriers generated in the semiconductor substrate underlying the thin layer in response to applied radiation diffuse to the region of opposite conductivity type and are sensed.
摘要翻译： 在一种导电类型和高电阻率的半导体材料的衬底（11）中，在衬底的主表面（15）附近提供具有相同导电性和低电阻率的薄层（13,14）。 相邻导电类型的区域（21）设置在邻近主表面的衬底中，以形成邻近薄层的PN结（22）。 在PN结上提供零偏置。 响应于施加的辐射而在薄层下面的半导体衬底中产生的少数电荷载流子扩散到相反导电类型的区域并被感测。
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3.发明授权Means of selecting low noise performance or low power dissipation in the analog front end of a custom integrated circuit 失效在定制集成电路的模拟前端选择低噪声性能或低功耗的手段公开(公告)号：US06426672B1
公开(公告)日：2002-07-30
申请号：US08919936
申请日：1997-08-28
IPC分类号： H03K190948
CPC分类号： H03F1/26 , H03F3/45183 , H03F3/72 , H03F2200/372 , H03F2203/45506 , H03F2203/45726
摘要： A signal processing circuit can be used to select between a high bias current and good noise performance or a low bias current and poorer noise performance. The circuit comprises an input device having high impedance and low noise characteristics. A first current source provides a minimal current level through the input device. Additional current sources provide additional current through the input device to improve noise performance of the circuit. The additional current sources can be switched into the circuit when improved noise performance is required, and switched out of the circuit to conserve power when improved noise performance is not required.
摘要翻译： 信号处理电路可用于选择高偏置电流和良好的噪声性能或低偏置电流和较差的噪声性能。 该电路包括具有高阻抗和低噪声特性的输入装置。 第一个电流源通过输入设备提供最小的电流电平。 额外的电流源通过输入设备提供额外的电流，以改善电路的噪声性能。 当需要改进的噪声性能时，额外的电流源可以切换到电路中，并且在不需要改进的噪声性能时从电路切换以节省功率。
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公开(公告)号：US4097886A
公开(公告)日：1978-06-27
申请号：US735024
申请日：1976-10-22
IPC分类号： H01L29/423 , H01L29/768 , H01L29/78 , G11C19/28 , H03H7/28
CPC分类号： H01L29/76891 , H01L29/42396
摘要： Geometries suitable for split or paired electrode structures of small effective dimensions which are readily implementable with a high degree of accuracy are provided.
摘要翻译： 提供了适用于能够以高精确度容易地实现的小有效尺寸的分离或成对电极结构的几何形状。
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5.发明授权High order sigma delta oversampled analog-to-digital converter integrated circuit network with minimal power dissipation and chip area requirements 失效高阶SIGMA DELTA OVERSAMPLED模拟数字转换器集成电路网络与最小功耗和芯片区域要求
公开(公告)号：US5065157A
公开(公告)日：1991-11-12
申请号：US505382
申请日：1990-04-06
摘要： An improved high order interpolative oversampled (sigma delta) analog-to-digital converter network including a plurality of cascade-coupled integrator stages is formed on a single integrated circuit chip in a manner that conserves power and chip area. Each integrator stage includes a differential amplifier, at least one input capacitor and at least one feedback capacitor. The power dissipation and occupied chip area are minimized by down-sizing the chip area occupied by the capacitors and differential amplifiers (op amps) in all but the first integrator stage. The high gain of the first integrator stage makes the noise contribution of subsequent integrator stages negligible so that the higher noise of the subsequent integrator stages is tolerable.
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公开(公告)号：US4178519A
公开(公告)日：1979-12-11
申请号：US934011
申请日：1978-08-16
IPC分类号： G11C19/28 , G11C27/04 , H01L29/768 , H01L27/02 , H01L29/78
CPC分类号： H01L29/76808 , G11C19/285 , G11C27/04
摘要： Input structures are described for sampling an analog signal and providing charge samples in accordance therewith to charge transfer devices.
摘要翻译： 描述了用于对模拟信号进行采样并根据其提供电荷样本的电荷转移装置的输入结构。
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公开(公告)号：US4302686A
公开(公告)日：1981-11-24
申请号：US162015
申请日：1980-06-23
IPC分类号： G11C19/28 , H01L27/105 , H01L29/78
CPC分类号： H01L27/1057 , G11C19/285 , G11C19/287
摘要： A charge transfer device is described for the conversion of a sequence of samples of a signal occurring at high frequency into simultaneous data samples occurring at a substantially lower frequency and substantially longer duration.
摘要翻译： 描述了一种电荷转移装置，用于将以高频发生的信号的样本序列转换成以基本上较低的频率和显着更长的持续时间发生的同时数据样本。
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公开(公告)号：US4165537A
公开(公告)日：1979-08-21
申请号：US934012
申请日：1978-08-16
IPC分类号： G11C11/56 , G11C19/28 , G11C27/04 , H01L21/339 , H01L29/762 , H01L29/768 , H03H11/26 , G11C27/00
CPC分类号： G11C19/285 , G11C27/04 , H01L29/76808
摘要： Input sampling circuits are described for converting an analog signal into charge samples for charge transfer devices.
摘要翻译： {PG，1描述了用于将模拟信号转换为电荷转移装置的电荷样本的输入采样电路。
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公开(公告)号：US4185318A
公开(公告)日：1980-01-22
申请号：US915784
申请日：1978-06-15
CPC分类号： G11C11/35
摘要： A conductor-insulator-semiconductor (CIS) structure for a random access surface charge memory system is disclosed. The memory system comprises an array of memory cells including charge storage regions, charge transfer regions and charge receive-source regions formed along the surface-adjacent portions of a semiconductor substrate. A charge-storage line insulatingly overlies the storage regions of a row of memory cells and a bit line, comprising an extended region of opposite-conductivity-type, interconnects the receive-source regions of the same memory cells. Addressing in the Y-direction (word selection) is provided by charge transfer lines insulatingly overlying the charge transfer regions of a column of memory cells. Selected memory cells are addressed for read and write purposes by first activating the word select line which makes available one cell in each row of the memory. The desired row is then selected by means external to the array of memory cells. All cells of the selected word line are refreshed, but only one cell is addressed for read and write purposes. Means for reading, writing and refreshing data in the memory system are also disclosed.
摘要翻译： 公开了一种用于随机存取面电荷存储器系统的导体 - 绝缘体半导体（CIS）结构。 存储器系统包括存储单元的阵列，包括沿着半导体衬底的表面相邻部分形成的电荷存储区域，电荷转移区域和电荷接收源区域。 电荷存储线绝缘地覆盖在存储单元行的存储区域和包括相反导电类型的扩展区域的位线，互连相同存储单元的接收源区域。 Y方向的寻址（字选择）由绝缘地覆盖存储单元列的电荷转移区域的电荷传输线提供。 所选择的存储单元通过首先激活字选择线来寻址以用于读和写目的，这使得在存储器的每一行中可用一个单元。 然后通过外部存储器单元阵列的方式选择所需的行。 所选字线的所有单元格被刷新，但仅读取和写入一个单元格。 还公开了用于在存储器系统中读取，写入和刷新数据的装置。
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公开(公告)号：US4126852A
公开(公告)日：1978-11-21
申请号：US787915
申请日：1977-04-15
申请人： Richard D. Baertsch
发明人： Richard D. Baertsch
摘要： A multiplying digital to analog converter providing a sequence of signal samples in which each sample represents the product of a respective sample of an analog input signal and a respective binary number is disclosed. The converter comprises a semiconductor device including a plurality of charge storage cells each paired with a respective digit of a binary number. The quantity of charge introduced into each of the storage regions is dependent on the sample of the analog signal and the presence of a "1" in the respective digit of the binary number. The product of the sample of the analog signal and the binary number is obtained by combining the charges so introduced into the storage regions.
摘要翻译： 公开了一种乘法数模转换器，其提供一系列信号样本，其中每个样本表示模拟输入信号的相应样本和相应二进制数的乘积。 该转换器包括一个包括多个电荷存储单元的半导体器件，每个电荷存储单元与二进制数的相应数字配对。 引入每个存储区域的电荷量取决于模拟信号的样本和二进制数的相应数字中存在“1”。 模拟信号的样本和二进制数的乘积通过将所引入的电荷组合到存储区域中来获得。
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