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1.发明授权Pipelined data cache with multiple ports and processor with load/store unit selecting only load or store operations for concurrent processing 失效具有多个端口和处理器的流水线数据高速缓存，加载/存储单元仅选择用于并发处理的加载或存储操作公开(公告)号：US06202139B1
公开(公告)日：2001-03-13
申请号：US09100291
申请日：1998-06-19
申请人： David B. Witt , James K. Pickett
发明人： David B. Witt , James K. Pickett
IPC分类号： G06F1300
CPC分类号： G11C7/1039 , G06F9/3824 , G06F9/3869 , G06F12/0853 , G06F12/0855 , G11C7/1072 , G11C8/16
摘要： A computer system includes a processor having a cache which includes multiple ports, although a storage array included within the cache may employ fewer physical ports than the cache supports. The cache is pipelined and operates at a clock frequency higher than that employed by the remainder of a microprocessor including the cache. In one embodiment, the cache preferably operates at a clock frequency which is at least a multiple of the clock frequency at which the remainder of the microprocessor operates. The multiple is equal to the number of ports provided on the cache (or the ratio of the number of ports provided on the cache to the number of ports provided internally, if more than one port is supported internally). Accordingly, the accesses provided on each port of the cache during a clock cycle of the microprocessor clock can be sequenced into the cache pipeline prior to commencement of the subsequent clock cycle. In one particular embodiment, the load/store unit of the microprocessor is configured to select only load memory operations or only store memory operations for concurrent presentation to the data cache. Accordingly, the data cache may be performing only reads or only writes to its internal array during a clock cycle. The data cache may implement several techniques for accelerating access time based upon this feature. For example, the bit lines within the data cache array may be only balanced between accesses instead of precharging (and potentially balancing).
摘要翻译： 计算机系统包括具有包括多个端口的高速缓存的处理器，尽管包含在高速缓存内的存储阵列可以采用比缓存支持更少的物理端口。 高速缓冲存储器是流水线的，并以比包括高速缓存的微处理器的其余部分所采用的时钟频率更高的时钟频率工作。 在一个实施例中，高速缓存优选地以至少为微处理器的其余部分工作的时钟频率的倍数的时钟频率操作。 该倍数等于缓存上提供的端口数（或缓存上提供的端口数与内部提供的端口数之间的比例，如果内部支持多个端口）。 因此，在微处理器时钟的时钟周期期间，在高速缓存的每个端口上提供的访问可以在随后的时钟周期开始之前被排序到高速缓存流水线中。 在一个具体实施例中，微处理器的加载/存储单元被配置为仅选择加载存储器操作或仅存储用于并发呈现到数据高速缓存的存储器操作。 因此，在时钟周期期间，数据高速缓存可以仅执行读取或仅执行对其内部阵列的写入。 基于该特征，数据高速缓存可以实现几种用于加速访问时间的技术。 例如，数据高速缓存阵列中的位线可以仅在访问之间进行平衡，而不是预充电（和潜在的平衡）。
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2.发明授权Prefetch unit for use with a cache memory subsystem of a cache memory hierarchy 有权预取单元，用于缓存存储器层次结构的高速缓存存储器子系统公开(公告)号：US07836259B1
公开(公告)日：2010-11-16
申请号：US10817693
申请日：2004-04-02
IPC分类号： G06F13/28
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A prefetch unit for use with a cache subsystem. The prefetch unit includes a stream storage coupled to a prefetch unit. The stream storage may include a plurality of locations configured to store a plurality of entries each corresponding to a respective range of prefetch addresses. The prefetch control may be configured to prefetch an address in response to receiving a cache access request including an address that is within the respective range of prefetch addresses of any of the plurality of entries.
摘要翻译： 用于缓存子系统的预取单元。 预取单元包括耦合到预取单元的流存储器。 流存储器可以包括被配置为存储多个条目的多个位置，每个条目对应于预取地址的相应范围。 预取控制可以被配置为响应于接收包括在多个条目中的任何一个的预取地址的相应范围内的地址的高速缓存访问请求来预取地址。
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公开(公告)号：US07089400B1
公开(公告)日：2006-08-08
申请号：US10347822
申请日：2003-01-21
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/30134 , G06F9/345 , G06F9/3834 , G06F9/3842
摘要： A processor may include a stack file and an execution core. The stack file may include an entry configured to store an addressing pattern and a tag. The addressing pattern identifies a memory location within the stack area of memory. The stack file may be configured to link a data value identified by the tag stored in the entry to the speculative result of a memory operation if the addressing pattern of the memory operation matches the addressing pattern stored in the entry. The execution core may be configured to access the speculative result when executing another operation that is dependent on the memory operation.
摘要翻译： 处理器可以包括堆栈文件和执行核心。 堆栈文件可以包括被配置为存储寻址模式和标签的条目。 寻址模式识别存储器堆栈区域内的存储器位置。 如果存储器操作的寻址模式与存储在条目中的寻址模式匹配，则堆栈文件可以被配置为将由条目中存储的标签识别的数据值链接到存储器操作的推测结果。 执行核心可以被配置为在执行取决于存储器操作的另一操作时访问推测结果。
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4.发明授权Microprocessor employing a performance throttling mechanism for power management 有权微处理器采用电源管理的性能调节机制公开(公告)号：US06826704B1
公开(公告)日：2004-11-30
申请号：US09802782
申请日：2001-03-08
申请人： James K. Pickett
发明人： James K. Pickett
IPC分类号： G06F126
CPC分类号： G06F9/30185 , G06F1/3203 , G06F1/3243 , G06F9/30152 , G06F9/3816 , G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3869 , Y02D10/152
摘要： A microprocessor includes a plurality of execution units each configured to execute instructions and an instruction dispatch circuit configured to dispatch instructions for execution by the plurality of execution units. A power management control unit includes a programmable unit for storing information specifying one or more reduced power modes. In the implementation of a first performance throttling technique, the power management control unit may be configured to cause the instruction dispatcher to limit the dispatch of instructions to a limited number of execution units. In the implementation of a second performance throttling technique, the power management control unit may be configured to limit the dispatch of instructions from the instruction dispatcher on every cycle, upon every other cycle, upon every third cycle, upon every fourth cycle, and so on. In the implementation of a third performance throttling technique, the power management control unit may be configured to control the dispatch of instructions from a floating-point scheduler to one or more floating-point execution pipelines.
摘要翻译： 微处理器包括：多个执行单元，每个执行单元被配置为执行指令;以及指令调度电路，被配置为分派由多个执行单元执行的指令。 功率管理控制单元包括用于存储指定一个或多个降低功率模式的信息的可编程单元。 在第一性能节流技术的实现中，功率管理控制单元可以被配置为使得指令调度器将指令的分派限制到有限数量的执行单元。 在第二性能节流技术的实现中，功率管理控制单元可以被配置为在每个周期，每三个周期，每四个周期等等的每个周期，限制来自指令分派器的指令的分派，等等 。 在第三性能调节技术的实现中，功率管理控制单元可以被配置为控制从浮点调度器到一个或多个浮点执行管线的指令的分派。
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5.发明授权
公开(公告)号：US6151662A
公开(公告)日：2000-11-21
申请号：US982720
申请日：1997-12-02
CPC分类号： G06F9/30192 , G06F12/0862 , G06F12/0888 , G06F9/30047 , G06F9/345 , G06F9/383 , G06F2212/6028
摘要： A microprocessor assigns a data transaction type to each instruction. The data transaction type is based upon the encoding of the instruction, and indicates an access mode for memory operations corresponding to the instruction. The access mode may, for example, specify caching and prefetching characteristics for the memory operation. The access mode for each data transaction type is selected to enhance the speed of access by the microprocessor to the data, or to enhance the overall cache and prefetching efficiency of the microprocessor by inhibiting caching and/or prefetching for those memory operations. Instead of relying on data memory access patterns and overall program behavior to determine caching and prefetching operations, these operations are determined on an instruction-by-instruction basis. Additionally, the data transaction types assigned to different instruction encodings may be revealed to program developers. Program developers may use the instruction encodings (and instruction encodings which are assigned to a nil data transaction type causing a default access mode) to optimize use of processor resources during program execution.
摘要翻译： 微处理器为每个指令分配数据事务类型。 数据交易类型基于指令的编码，并且指示对应于指令的存储器操作的访问模式。 访问模式可以例如指定用于存储器操作的缓存和预取特性。 选择每个数据事务类型的访问模式以增强微处理器对数据的访问速度，或通过禁止对这些存储器操作的高速缓存和/或预取来增强微处理器的总体缓存和预取效率。 不依赖数据存储器访问模式和整体程序行为来确定高速缓存和预取操作，而是依据逐个指令来确定这些操作。 此外，分配给不同指令编码的数据事务类型可能会显示给程序开发人员。 程序开发人员可以使用指令编码（以及分配给导致默认访问模式的零数据事务类型的指令编码）来优化程序执行期间处理器资源的使用。
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公开(公告)号：US6079006A
公开(公告)日：2000-06-20
申请号：US52183
申请日：1998-03-31
申请人： James K. Pickett
发明人： James K. Pickett
CPC分类号： G06F12/0862 , G06F9/3455 , G06F9/3802 , G06F9/3806 , G06F9/3828 , G06F9/383 , G06F9/3832 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F2212/6026
摘要： A data prediction structure is provided for a superscalar microprocessor. The data prediction structure stores base addresses and stride values in a prediction array. The base address and the stride value from a location within the data prediction structure indexed by an instruction address are added to form a data prediction address which is then used to fetch data bytes into a reservation station storing an associated instruction. If the data associated with an operand address calculated by an associated functional unit resides in the reservation station, the clock cycles used to perform the load operation have occurred before the instruction reached the reservation station. Additionally, the base address is updated to the address generated by executing an instruction each time the instruction is executed, and the stride value is updated when the data prediction address is found to be incorrect.
摘要翻译： 为超标量微处理器提供数据预测结构。 数据预测结构将基地址和步幅值存储在预测数组中。 添加由指令地址索引的数据预测结构内的位置的基地址和步幅值，以形成数据预测地址，然后将其用于将数据字节提取到存储相关指令的保留站。 如果与由关联的功能单元计算的操作数地址相关联的数据驻留在保留站中，则在指令到达保留站之前已经发生用于执行加载操作的时钟周期。 此外，基地址被更新为每次执行指令时执行指令而生成的地址，并且当发现数据预测地址不正确时更新步幅值。
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7.发明授权Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction 失效用于存储对应于由多个并行记录指令更新的寄存器的推测结果的推测寄存器存储器
公开(公告)号：US5933618A
公开(公告)日：1999-08-03
申请号：US550218
申请日：1995-10-30
CPC分类号： G06F9/3812 , G06F12/0804 , G06F12/0846 , G06F12/0864 , G06F9/30054 , G06F9/30152 , G06F9/3806 , G06F9/3814 , G06F9/3832 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3863
摘要： A microprocessor including a reorder buffer configured to store speculative register values regarding a particular register is provided. One value is stored for each set of concurrently decoded instructions which are outstanding within the microprocessor, reflecting the updates of each instruction within the set which updates the register. Additionally, the reorder buffer stores a set of constants indicative of the modification of the register by each instruction within the set of concurrently decoded instructions. Recovery from a mispredicted branch instruction (or from an instruction which causes an exception, a TRAP instruction, or an interrupt) may be achieved by utilizing the constants to adjust the result generated for the set of concurrently decoded instructions including the mispredicted branch instruction. The constants generated to indicate the modifications of the particular register may additionally allow multiple instructions having a dependency for the particular register to execute in parallel.
摘要翻译： 提供了一种微处理器，其包括配置为存储关于特定寄存器的推测寄存器值的重排序缓冲器。 对于在微处理器内未完成的每组并行解码的指令存储一个值，反映了更新寄存器的集合内的每个指令的更新。 此外，重排序缓冲器存储指示该并发解码指令集内的每个指令对寄存器进行修改的一组常数。 可以通过利用常数来调整针对包括错误预测的分支指令的并行解码指令集合生成的结果来实现从错误预测的分支指令（或来自导致异常，TRAP指令或中断的指令）的恢复。 为了指示特定寄存器的修改产生的常数可另外允许具有对特定寄存器的依赖性的多个指令并行执行。
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8.发明授权Speculation pointers to identify data-speculative operations in microprocessor 有权用于识别微处理器中数据推测操作的推测指针公开(公告)号：US07266673B2
公开(公告)日：2007-09-04
申请号：US10429159
申请日：2003-05-02
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3865
摘要： A microprocessor may include a retire queue and one or more data speculation verification units. The data speculation verification units are each configured to verify data speculation performed on operations. Each data speculation verification unit generates a respective speculation pointer identifying outstanding operations on which data speculation has been verified by that data speculation verification unit. The retire queue is configured to selectively retire operations dependent on the speculation pointer received from each of the data speculation verification units.
摘要翻译： 微处理器可以包括退出队列和一个或多个数据推测验证单元。 数据推测验证单元被配置为验证对操作执行的数据推测。 每个数据推测验证单元产生识别由该数据推测验证单元已经对其进行数据猜测的未完成操作的各个推测指针。 退休队列被配置为根据从每个数据推测验证单元接收的推测指针选择性地退出操作。
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公开(公告)号：US07165167B2
公开(公告)日：2007-01-16
申请号：US10458457
申请日：2003-06-10
IPC分类号： G06F9/24
CPC分类号： G06F9/3842 , G06F9/3826 , G06F9/3832 , G06F9/3834 , G06F9/3861
摘要： A microprocessor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.
摘要翻译： 微处理器可以包括被配置为发布操作的调度器和被配置为执行由调度器发出的存储器操作的加载存储单元。 加载存储单元被配置为存储识别发送到加载存储单元的存储器操作的信息。 响应于检测到所发出的存储器操作之一的不正确的数据推测，加载存储单元被配置为通过向调度器提供指示来重播所发布的存储器操作中的至少一个。 调度器被配置为响应地重新发出由加载存储单元识别的存储器操作。
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公开(公告)号：US6106573A
公开(公告)日：2000-08-22
申请号：US311788
申请日：1999-05-14
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/3648 , G06F11/348
摘要： A microprocessor implements an instruction tracing mechanism that saves the state of the microprocessor without special hardware. Prior to the execution of a traced instruction, a trace microcode routine is implemented that saves the state of the microprocessor to external memory. The state information saved by the trace microcode routine varies depending upon the amount of data needed by the end user. After the state of the processor has been saved, the trace instruction is executed. State information that changed during the execution of the trace instruction is saved to memory prior to a subsequent instruction. The trace instruction mechanism advantageously requires minimal special hardware and expedites the saving of the processor state information.
摘要翻译： 微处理器实现了一种指令跟踪机制，可以在没有特殊硬件的情况下保存微处理器的状态。 在执行跟踪指令之前，实现了将微处理器的状态保存到外部存储器的跟踪微代码程序。 跟踪微代码程序保存的状态信息取决于最终用户所需的数据量。 处理器状态保存完毕后，执行跟踪指令。 在执行跟踪指令期间更改的状态信息在后续指令之前被保存到存储器中。 跟踪指令机制有利地需要最小的特殊硬件并且加快处理器状态信息的保存。
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