公开(公告)号：US06670242B1

公开(公告)日：2003-12-30

申请号：US09651447

申请日：2000-08-30

申请人： David Charles Brady ,  Yi Ma ,  Pradip Kumar Roy

发明人： David Charles Brady ,  Yi Ma ,  Pradip Kumar Roy

IPC分类号： H01L21336

CPC分类号： C30B29/06 ,  C30B33/005 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/518

摘要： A method for making an integrated circuit device includes forming source and drain regions in a semiconductor substrate and defining a channel region therebetween, forming a graded, grown, gate oxide layer adjacent the channel region, forming a nitride layer adjacent the gate oxide layer, and forming a gate electrode layer adjacent the nitride layer. The gate oxide layer may be formed by growing a first oxide portion by upwardly ramping the channel region to a first temperature lower than a glass transition temperature, and exposing the channel region to an oxidizing ambient at the first temperature and for a first time period. A second oxide portion may be grown between the first oxide portion and the channel region by exposing the channel region to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period so that the second oxide portion has a thickness in a range of about 2% to about 75% of a total thickness of the gate oxide layer. Forming the nitride layer may include forming a non-stoichiometric nitride layer, and the nitride layer is preferably formed to have a thickness of less than about 15 Å. The nitride layer reduces penetration of a dopant, such as boron, into the gate oxide layer.

摘要翻译： 一种制造集成电路器件的方法包括：在半导体衬底中形成源区和漏极区，并在其间限定沟道区，形成与沟道区相邻的渐变，生长的栅极氧化层，形成与栅极氧化物层相邻的氮化物层，以及 形成与氮化物层相邻的栅电极层。 栅极氧化物层可以通过使沟道区域向上斜坡至低于玻璃化转变温度的第一温度并且使第一氧化物部分在第一温度和第一时间段内将沟道区域暴露于氧化环境而形成第一氧化物部分。 在第二氧化物部分可以在第一氧化物部分和沟道区域之间生长，通过在高于玻璃化转变温度的第二温度下将沟道区域暴露于氧化环境第二时间段，使得第二氧化物部分的厚度为 栅极氧化物层的总厚度的约2％至约75％的范围。 形成氮化物层可以包括形成非化学计量的氮化物层，并且氮化物层优选形成为具有小于约的厚度。 氮化物层将诸如硼的掺杂剂的渗透减少到栅极氧化物层中。

公开(公告)号：US06320238B1

公开(公告)日：2001-11-20

申请号：US09339895

申请日：1999-06-25

申请人： Isik C. Kizilyalli ,  Yi Ma ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy

发明人： Isik C. Kizilyalli ,  Yi Ma ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/94

摘要： The present invention relates to a gate stack structure having a dielectric material layer disposed on a substrate with a gate electrode disposed thereon. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.2 nm or less and includes at least one layer other than silicon dioxide. Furthermore, the dielectric material layer of the present invention enables device scaling and provides (1) decreased leakage current and improved tunneling voltage compared to a conventional gate dielectric; and (2) avoids the perils of ultra-thin silicon dioxide when used exclusively as the gate dielectric.

摘要翻译： 本发明涉及一种具有设置在其上设置有栅电极的基板上的电介质材料层的栅极堆叠结构。 在一个示例性实施例中，电介质材料层具有2.2nm或更小的等效电气厚度，并且包括除二氧化硅之外的至少一个层。 此外，本发明的电介质材料层能够进行器件定标，并且与常规栅极电介质相比提供（1）降低的漏电流和改善的隧穿电压; 和（2）当专门用作栅极电介质时，避免超薄二氧化硅的危险。

公开(公告)号：US6074933A

公开(公告)日：2000-06-13

申请号：US924730

申请日：1997-09-05

申请人： Yi Ma ,  Pradip Kumar Roy

发明人： Yi Ma ,  Pradip Kumar Roy

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/823878 ,  H01L21/76202

摘要： Undesirable birds beak pull back due to ion implant damage is alleviated by additional oxide growth.

摘要翻译： 由于离子注入引起的不希望的鸟喙拉回由于额外的氧化物生长而减轻。

公开(公告)号：US5981403A

公开(公告)日：1999-11-09

申请号：US977319

申请日：1997-11-24

申请人： Yi Ma ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy

发明人： Yi Ma ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L21/32 ,  H01L21/762 ,  H01L29/51 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28202 ,  H01L21/3145 ,  H01L21/3185 ,  H01L21/32 ,  H01L21/76202 ,  H01L29/513 ,  H01L29/518

摘要： A semiconductor device process for forming a multilayered nitride structure. The nitride is used as either isolation or as part of a dielectric structure. The deposition rate for the nitride is varied to form a multilayered structure with stress accommodation at the interface between sub-layers in the multilayer structure. In addition, the sub-layered structure reduces pin-holes and microcracks in the nitride film and improves the overall uniformity in thickness of the final nitride film.

摘要翻译： 一种用于形成多层氮化物结构的半导体器件工艺。 氮化物被用作隔离或作为电介质结构的一部分。 改变氮化物的沉积速率以形成在多层结构中的子层之间的界面处具有应力调节的多层结构。 此外，亚层结构减少氮化物膜中的针孔和微裂纹，并且改善最终氮化物膜的厚度的总体均匀性。

公开(公告)号：US5960302A

公开(公告)日：1999-09-28

申请号：US775790

申请日：1996-12-31

申请人： Yi Ma ,  Pradip Kumar Roy ,  Kevin Yun-Kang Wu

发明人： Yi Ma ,  Pradip Kumar Roy ,  Kevin Yun-Kang Wu

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/3205

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

摘要： A composite 3-layer gate dielectric is disclosed. The upper and lower layers have a concentration of nitrogen atoms, while the middle layer has very few nitrogen atoms. The presence of the nitrogen atoms in the top sublayers provides resistance to boron diffusion from the top conductive layer and plasma damage during polysilicon gate stack formation and the presence of nitrogen in the bottom sublayer near the silicon-dielectric interface improves wearout, endurance, resistance to current stress and electron traps.

摘要翻译： 公开了复合三层栅极电介质。 上层和下层具有氮原子的浓度，而中间层具有非常少的氮原子。 顶层子层中氮原子的存在提供了对顶部导电层的硼扩散的阻力和在多晶硅栅叠层形成期间的等离子体损伤，并且在硅 - 介电界面附近的底层子层中存在氮，从而改善了耐磨性，耐久性 电流应力和电子阱。

公开(公告)号：US06147388A

公开(公告)日：2000-11-14

申请号：US977318

申请日：1997-11-24

申请人： Yi Ma ,  Sailesh Mansinh Merchant ,  Minseok Oh ,  Pradip Kumar Roy

发明人： Yi Ma ,  Sailesh Mansinh Merchant ,  Minseok Oh ,  Pradip Kumar Roy

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/324 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/43 ,  H01L29/49 ,  H01L21/283 ,  H01L21/265

CPC分类号： H01L21/324 ,  H01L21/28061 ,  H01L29/4925 ,  H01L29/4941

摘要： A CMOS gate structure comprises a multilayered polysilicon structure and a deposited silicide layer, with a nitridized silicide barrier layer formed therebetween. The multilayered polysilicon will exhibit a relatively large grain size and uniform structure. The deposited silicide layer is annealed to mimic the polysilicon grain size and structure. The combination of the tailored grain structure with the intermediate barrier layer results in a gate structure that is essentially impervious to subsequent dopant diffusions.

摘要翻译： CMOS栅极结构包括多层多晶硅结构和沉积的硅化物层，其间形成氮化硅化物阻挡层。 多层多晶硅将具有相对较大的晶粒尺寸和均匀的结构。 将沉积的硅化物层退火以模拟多晶硅晶粒尺寸和结构。 定制的晶粒结构与中间阻挡层的组合导致栅极结构，其基本上不渗透随后的掺杂剂扩散。

公开(公告)号：US5908312A

公开(公告)日：1999-06-01

申请号：US864220

申请日：1997-05-28

申请人： Kin Ping Cheung ,  Steven James Hillenius ,  Chun-Ting Liu ,  Yi Ma ,  Pradip Kumar Roy

发明人： Kin Ping Cheung ,  Steven James Hillenius ,  Chun-Ting Liu ,  Yi Ma ,  Pradip Kumar Roy

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/316 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/518 ,  H01L21/26506

摘要： A method of preventing diffusion penetration of the dopant used to dope polysilicon gate material in a MOSFET is disclosed. Atomic nitrogen is introduced into the substrate prior to gate oxide growth. The nitrogen later diffuses upward into the gate oxide and blocks subsequent ion implanted gate dopants from penetrating to the substrate. Low dosages of atomic nitrogen implantation, while not significantly affecting gate oxide growth rate, produce significant improvements in the damage immunity of thin gate oxides.

摘要翻译： 公开了一种防止用于掺杂MOSFET中的多晶硅栅极材料的掺杂剂的扩散渗透的方法。 在栅极氧化物生长之前将原子氮引入衬底中。 然后氮气向上扩散到栅极氧化物中，并阻止随后的离子注入的栅极掺杂剂渗透到衬底。 低剂量的原子氮注入虽然没有显着影响栅极氧化物的生长速率，但对薄栅氧化物的损伤免疫力产生了显着的改善。

公开(公告)号：US06548854B1

公开(公告)日：2003-04-15

申请号：US08995435

申请日：1997-12-22

申请人： Isik C. Kizilyalli ,  Yi Ma ,  Pradip Kumar Roy

发明人： Isik C. Kizilyalli ,  Yi Ma ,  Pradip Kumar Roy

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517

摘要： A gate or capacitor insulator structure using a first grown oxide layer, a high-k dielectric material on the grown oxide layer, and a deposited oxide layer on the high-k dielectric material. The deposited oxide layer is preferably a densified deposited oxide layer. A conducting layer, such as a gate or capacitor plate, may overlay the densified oxide layer.

摘要翻译： 使用第一生长氧化物层，生长的氧化物层上的高k电介质材料和高k电介质材料上的沉积氧化物层的栅极或电容器绝缘体结构。 沉积的氧化物层优选是致密化的沉积氧化物层。 诸如栅极或电容器板的导电层可以覆盖致密的氧化物层。

公开(公告)号：US06207586B1

公开(公告)日：2001-03-27

申请号：US09334911

申请日：1999-06-17

申请人： Yi Ma ,  Pradip Kumar Roy

发明人： Yi Ma ,  Pradip Kumar Roy

IPC分类号： H01L2131

CPC分类号： H01L21/0217 ,  C23C16/345 ,  C23C16/56 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/3145 ,  H01L21/3185

摘要： A method for making an oxide/nitride stacked layer makes the nitride layer defective so that it is semi-transparent or permeable to oxygen. The method includes first forming an oxide layer on a semiconductor substrate. The defective nitride layer is formed on the oxide layer using direct plasma enhanced chemical vapor deposition. The defective nitride layer is formed while exposing the plasma with a low energy magnetic field for providing a uniform energy distribution across a surface of the oxide layer. A resulting distribution of thicknesses of the defective nitride layer has a standard deviation less than about 1.5% across a wafer. The defective nitride layer is permeable to oxygen so that when the semiconductor substrate is annealed, the interface trap sites are significantly reduced or eliminated.

摘要翻译： 制造氧化物/氮化物堆叠层的方法使得氮化物层有缺陷，使得其为半透明或可渗透氧。 该方法包括首先在半导体衬底上形成氧化物层。 使用直接等离子体增强化学气相沉积在氧化物层上形成有缺陷的氮化物层。 形成有缺陷的氮化物层，同时以低能磁场暴露等离子体，以便在氧化物层的表面上提供均匀的能量分布。 所形成的缺陷氮化物层的厚度的分布在晶片上具有小于约1.5％的标准偏差。 有缺陷的氮化物层对氧是可渗透的，使得当半导体衬底退火时，界面陷阱位置被显着地减少或消除。

公开(公告)号：US08818132B2

公开(公告)日：2014-08-26

申请号：US13310729

申请日：2011-12-03

申请人： Zhengdong Zhang ,  Yasuyuki Matsushita ,  Yi Ma

发明人： Zhengdong Zhang ,  Yasuyuki Matsushita ,  Yi Ma

IPC分类号： G06K9/36 ,  G06T7/00

CPC分类号： G06T7/0018 ,  G06T7/80 ,  G06T2207/20104 ,  H04N17/002

摘要： A “Camera Calibrator” provides various techniques for recovering intrinsic camera parameters and distortion characteristics by processing a set of one or more input images. These techniques are based on extracting “Transform Invariant Low-Rank Textures” (TILT) from input images using high-dimensional convex optimization tools for matrix rank minimization and sparse signal recovery. The Camera Calibrator provides a simple, accurate, and flexible method to calibrate intrinsic parameters of a camera even with significant lens distortion, noise, errors, partial occlusions, illumination and viewpoint change, etc. Distortions caused by the camera can then be automatically corrected or removed from images. Calibration is achieved under a wide range of practical scenarios, including using multiple images of a known pattern, multiple images of an unknown pattern, single or multiple images of multiple patterns, etc. Significantly, calibration is achieved without extracting or manually identifying low-level features such as corners or edges from the calibration images.

摘要翻译： “相机校准器”提供了通过处理一组一个或多个输入图像来恢复本征相机参数和失真特性的各种技术。 这些技术基于使用用于矩阵秩最小化和稀疏信号恢复的高维凸优化工具从输入图像中提取“变换不变低阶纹理”（TILT）。 相机校准器提供了一种简单，准确和灵活的校准相机内在参数的方法，即使有明显的镜头失真，噪点，错误，部分遮挡，照明和视点更改等。然后可以自动更正相机造成的失真或 从图像中删除 在广泛的实际情况下实现校准，包括使用已知图案的多个图像，未知图案的多个图像，多个图案的单个或多个图像等。显着地，在不提取或手动识别低级别的情况下实现校准 特征如校准图像的拐角或边缘。