公开(公告)号：US5986469A

公开(公告)日：1999-11-16

申请号：US932890

申请日：1997-09-17

申请人： David D. Eaton ,  Paige A. Kolze ,  James M. Apland

发明人： David D. Eaton ,  Paige A. Kolze ,  James M. Apland

IPC分类号： H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： A programmable integrated circuit (see FIG. 9) has a plurality of L-shaped programming power buses (for example, 126, 130, 129 and 127) that extend along sides of the integrated circuit. Each L-shaped programming power bus extends along two adjacent sides of the integrated circuit such that legs of two L-shaped programming power buses extend along each of the sides. There are four pluralities of programming drivers (for example, 110, 117, 115 and 112), one plurality being associated with each of the four sides. There are also four programming current multiplexers (for example, 118, 125, 123 and 120), one associated with each of the sides. A programming driver of one of the plurality of programming drivers is selectively couplable to one of the two L-shaped programming power bus legs that extends along the associated side of the integrated circuit via the programming current multiplexer associated with that side. Additional pluralities of programming drivers and additional programming current multiplexers can be provided.

摘要翻译： 可编程集成电路（见图9）具有沿着集成电路的侧面延伸的多个L形编程电源总线（例如，126,130,129和127）。 每个L形编程电源总线沿着集成电路的两个相邻侧延伸，使得两个L形编程电源总线的脚沿着每个侧面延伸。 有四种编程驱动程序（例如，110,117,115和112），一个与四个方面中的每一个相关联。 还有四个编程电流多路复用器（例如，118,125,123和120），一个与每个侧面相关联。 多个编程驱动器之一的编程驱动器可选择性地耦合到两个L形编程功率总线支路中的一个，其经由与该侧相关联的编程电流复用器沿着集成电路的相关侧延伸。 可以提供额外的多个编程驱动器和附加的编程电流多路复用器。

公开(公告)号：US6081129A

公开(公告)日：2000-06-27

申请号：US931893

申请日：1997-09-17

申请人： James M. Apland ,  Paige A. Kolze

发明人： James M. Apland ,  Paige A. Kolze

IPC分类号： H02H9/00 ,  H03K17/22 ,  H03K19/177 ,  H01L25/00

CPC分类号： H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. To test the integrity of programming conductors, programming transistors, routing wire segments and a combinatorial portion of a logic module of the unprogrammed FPGA (see FIG. 16), a combination of digital logic values is supplied onto the inputs of the combinatorial portion in a test mode. A defect is determined to exist if the correct digital value is not then output by the combinatorial portion. The digital value output by the combinatorial portion is captured in the flip-flop of the logic module and is shifted out of the FPGA in a scan out test mode. A programming transistor, programming conductor and routing wire segment structure is also disclosed which facilitates such testing. In one embodiment (see FIG. 15), the gate of no programming transistor coupled to an output routing wire segment of the logic module (such as transistor 216) is permanently connected to the gate of any programming transistor coupled to an input routing wire segment of the logic module (such as transistors 200, 201 and 202).

摘要翻译： 公开了一种采用反熔丝的现场可编程门阵列（FPGA）的编程架构。 为了测试编程导体，编程晶体管，布线线段和未编程FPGA（参见图16）的逻辑模块的组合部分的完整性，数字逻辑值的组合被提供到组合部分的输入端 测试模式。 如果正确的数字值不由组合部分输出，则确定存在缺陷。 由组合部分输出的数字值被捕获在逻辑模块的触发器中，并以扫描输出测试模式从FPGA中移出。 还公开了编程晶体管，编程导体和布线线段结构，其有助于这种测试。 在一个实施例中（参见图15），耦合到逻辑模块（例如晶体管216）的输出布线线段的无编程晶体管的栅极永久连接到耦合到输入布线线段的任何编程晶体管的栅极 的逻辑模块（例如晶体管200,201和202）。

公开(公告)号：US6127845A

公开(公告)日：2000-10-03

申请号：US112700

申请日：1998-07-08

申请人： Paige A. Kolze ,  Andre Stolmeijer ,  David D. Eaton

发明人： Paige A. Kolze ,  Andre Stolmeijer ,  David D. Eaton

IPC分类号： H01L21/8234 ,  H01L27/118 ,  H01L25/00 ,  G06F7/38

CPC分类号： H01L21/823462 ,  H01L27/11807

摘要： In a programmable device employing antifuses, first digital logic transistors the gates of which will experience a programming voltage Vpp have a greater gate insulator thickness than do second digital logic transistors the gates of which will not experience the programming voltage. The first digital logic transistors may be logic module input device transistors. The first digital logic transistors may be transistors coupled to an enable input lead where the enable input lead is couplable to a tie-high conductor or to a tie-low conductor depending on which of two antifuses is programmed.

摘要翻译： 在采用反熔丝的可编程器件中，其栅极经历编程电压Vpp的第一数字逻辑晶体管具有比其门不会经历编程电压的第二数字逻辑晶体管更大的栅绝缘体厚度。 第一数字逻辑晶体管可以是逻辑模块输入器件晶体管。 第一数字逻辑晶体管可以是耦合到使能输入引线的晶体管，其中根据两个反熔丝中的哪一个被编程，使能输入引线可以连接到连接导体或连接低导体。

公开(公告)号：US06169416A

公开(公告)日：2001-01-02

申请号：US09145581

申请日：1998-09-01

申请人： David D. Eaton ,  Paige A. Kolze

发明人： David D. Eaton ,  Paige A. Kolze

IPC分类号： H03K19173

CPC分类号： H03K19/17748 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： The programmable logic of a programmable device is sectioned into four logic regions. Each logic region includes logic elements and a programmable interconnect structure employing antifuses for programmably interconnecting selected ones of those logic elements. Programming conductors for supplying programming current to antifuses of a logic region extend across the logic region but do not extend across other logic regions. Similarly, programming control conductors that control programming transistors of the logic region extend across the logic region but do not extend across other logic regions. The programmable device structure allows four antifuses to be programmed simultaneously, one antifuse in each logic region. An antifuse can be selected for simultaneous programming from a logic region, irrespective of the other three antifuses that are or may be selected for simultaneous programming from the other three logic regions. Four programming current multiplexers and four programming buses are provided for each logic region so that the programming current that programs each antifuse flows from a separate input terminal. The resistance of the programming conductors is reduced by the use of parallel strips of metal in multiple metal layers.

摘要翻译： 可编程器件的可编程逻辑被分为四个逻辑区域。 每个逻辑区域包括逻辑元件和采用反熔丝的可编程互连结构，以可编程地互连那些逻辑元件中的选定的逻辑元件。 用于向逻辑区域的反熔点提供编程电流的编程导体跨越逻辑区域延伸，但不延伸到其他逻辑区域。 类似地，控制逻辑区域的编程晶体管的编程控制导体跨越逻辑区域延伸，但不跨越其它逻辑区域延伸。 可编程器件结构允许在每个逻辑区域中同时编程四个反熔丝，一个反熔丝。 可以选择反熔丝以用于从逻辑区域进行同时编程，而不管其他三个反熔丝是否来自其他三个逻辑区域也可以被选择用于同时编程。 为每个逻辑区域提供四个编程电流复用器和四个编程总线，使得编程每个反熔丝的编程电流从单独的输入端子流出。 通过在多个金属层中使用平行的金属条来减少编程导体的电阻。

公开(公告)号：US6157207A

公开(公告)日：2000-12-05

申请号：US76367

申请日：1998-05-11

申请人： David D. Eaton ,  Sudarshan Varshney ,  Paige A. Kolze

发明人： David D. Eaton ,  Sudarshan Varshney ,  Paige A. Kolze

IPC分类号： H01L21/8234 ,  H01L27/118 ,  G06F7/38 ,  H03K19/177

CPC分类号： H01L27/11807 ,  H01L21/823462

摘要： To protect logic module output devices from high voltages, logic modules are not powered during antifuse programming. In some embodiments, two separate power input terminals VCC1 and VCC2 are provided: power input terminal VCC1 being coupled to power the logic modules, and power input terminal VCC2 being coupled to power the programming control circuitry. Power terminal VCC1 is left floating or is grounded during antifuse programming such that the logic modules are not powered but such that the programming circuitry is powered during antifuse programming via the second power terminal VCC2. Logic module output protection transistors are not required nor is the associated charge pump. Because the logic module input devices are not powered, a current surge through the input devices on power up does not occur and an internal disable signal and associated circuitry is not required. In one embodiment, the field programmable gate array is made smaller because it has no internal disable signal and associated circuitry, no logic module output protection transistors, and no charge pump that operates during normal circuit operation. In embodiments, power input terminal VCC2 is a high voltage compatible power input terminal.

摘要翻译： 为了保护逻辑模块输出设备免受高电压的影响，逻辑模块在反熔丝编程期间未通电。 在一些实施例中，提供两个单独的电源输入端子VCC1和VCC2：电源输入端子VCC1被耦合以对逻辑模块供电，并且电源输入端子VCC2被耦合以对编程控制电路供电。 电源端子VCC1在反熔丝编程期间处于悬空状态或接地状态，使得逻辑模块未通电，而使编程电路在反熔丝编程期间通过第二电源端子VCC2供电。 不需要逻辑模块输出保护晶体管，也不需要相关的电荷泵。 由于逻辑模块输入设备未通电，所以不会在上电时通过输入设备产生电流浪涌，并且不需要内部禁用信号和相关电路。 在一个实施例中，由于现场可编程门阵列没有内部禁用信号和相关联的电路，没有逻辑模块输出保护晶体管，并且没有在正常电路操作期间操作的电荷泵，所以现场可编程门阵列被制造得更 在实施例中，电源输入端子VCC2是高电压兼容电力输入端子。

公开(公告)号：US08786310B1

公开(公告)日：2014-07-22

申请号：US13588647

申请日：2012-08-17

申请人： Weiguang Lu ,  Paige A. Kolze ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Chen W. Tseng

发明人： Weiguang Lu ,  Paige A. Kolze ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Chen W. Tseng

IPC分类号： H01L25/00 ,  H03K19/173 ,  G06F7/38 ,  G06F17/50

CPC分类号： G06F7/38 ,  G06F17/5027 ,  H01L25/00 ,  H01L2924/0002 ,  H03K19/173 ,  H03K19/17756 ,  H03K19/1776 ,  H01L2924/00

摘要： Approaches for partially reconfiguring a frame are disclosed. In one approach, a circuit arrangement includes programmable resources, frames of configuration memory cells, and partial configuration control memory cells. Each frame includes a plurality of subsets of configuration memory cells, and each subset configures one of the programmable resources. Each partial configuration control memory cell is coupled to a respective one of the subsets. Responsive to a first partial bitstream that includes a quantity of configuration data for all the subsets of configuration cells of a first frame of the plurality of frames, each subset of the configuration memory cells of the first frame is configurable or not configurable responsive to the state of the associated partial configuration control memory cell.

摘要翻译： 公开了部分重新配置帧的方法。 在一种方法中，电路装置包括可编程资源，配置存储单元的帧和部分配置控制存储单元。 每个帧包括配置存储器单元的多个子集，并且每个子集配置可编程资源之一。 每个部分配置控制存储器单元耦合到相应的一个子集。 响应于第一部分比特流，其包括多个帧的第一帧的配置单元的所有子集的配置数据量，第一帧的配置存储器单元的每个子集可配置或不可配置，以响应于状态 的相关部分配置控制存储单元。

公开(公告)号：US6018251A

公开(公告)日：2000-01-25

申请号：US931896

申请日：1997-09-17

申请人： Paige A. Kolze

发明人： Paige A. Kolze

IPC分类号： H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： A programmable integrated circuit (see FIG. 18) includes a plurality of interface cells with programmable antifuses disposed on a branch of a routing conductor. The routing conductor extends in a first direction and is coupled to one terminal of a programming transistor. The other terminal of the programming transistor is coupled to a programming driver via a programming conductor that extends in the first direction. The branch of the routing conductor crosses a plurality of routing wire segments of one of the interface cells, where programmable antifuses are disposed to couple the branch of the routing conductor to one or more of the routing wire segments. The routing wire segments extend parallel to one another in the first direction and are each coupled to a first terminal of separate programming transistors. The second terminals of the programming transistors are coupled to programming drivers via programming conductors that extend in a second direction, which is perpendicular to the first direction. Thus, the programming drivers for the routing wire segments and the routing conductor are positioned in different locations. Accordingly, when an antifuse is programming to couple the branch of the routing conductor with one of the routing wire segments, the two programming drivers are controlled by two different programming control shift registers.

摘要翻译： 可编程集成电路（参见图18）包括多个具有设置在布线导体的分支上的可编程反熔丝的接口单元。 布线导体沿第一方向延伸并且耦合到编程晶体管的一个端子。 编程晶体管的另一个端子通过在第一方向上延伸的编程导体耦合到编程驱动器。 布线导体的分支穿过接口单元之一的多个布线线段，其中设置可编程反熔丝以将布线导体的分支连接到一个或多个布线线段。 路由线段在第一方向上彼此平行延伸，并且各自耦合到单独编程晶体管的第一端。 编程晶体管的第二端子经由编程导体耦合到编程驱动器，编程导体在垂直于第一方向的第二方向上延伸。 因此，路由线段和路由导体的编程驱动器位于不同的位置。 因此，当反熔丝被编程以将布线导体的分支与布线线段中的一个耦合时，两个编程驱动器由两个不同的编程控制移位寄存器控制。

公开(公告)号：US6028444A

公开(公告)日：2000-02-22

申请号：US771471

申请日：1996-12-20

申请人： Richard J. Wong ,  Paige A. Kolze

发明人： Richard J. Wong ,  Paige A. Kolze

IPC分类号： H02H9/00 ,  H03K17/22 ,  H03K19/177 ,  H03K19/173

CPC分类号： H03K17/223 ,  H03K19/1778

摘要： Internal net drivers of a field programmable gate array are laid out with additional transistors to increase current drive capability at low supply voltages when a low supply voltage mask option is used. When a high supply voltage mask option is used, the additional transistors are not used in this way and the net drivers do not provide additional switching current drive capability. In some embodiments, were a low supply voltage mask option net driver operated at the high supply voltage, an impermissibly large switching current would flow through a programmed antifuse in a net coupled to the output of the net driver.

摘要翻译： 当使用低电源电压掩模选项时，现场可编程门阵列的内部网络驱动器布置有额外的晶体管，以在低电源电压下增加电流驱动能力。 当使用高电源电压掩模选项时，不以这种方式使用附加晶体管，并且网络驱动器不提供额外的开关电流驱动能力。 在一些实施例中，是在高电源电压下操作的低电源电压掩模选项网络驱动器，不可允许的大开关电流将流过耦合到网络驱动器的输出的网络中的经编程的反熔丝。

公开(公告)号：US5859543A

公开(公告)日：1999-01-12

申请号：US931895

申请日：1997-09-17

申请人： Paige A. Kolze

发明人： Paige A. Kolze

IPC分类号： H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： A programmable integrated circuit such as a field programmable gate array (see FIG. 3) has a few long routing wire segments for transmitting signals long distances across the integrated circuit. These long routing wire segments can be coupled together with programmed antifuses. A high-drive output driver may be used to drive signals a long distance through such coupled together long routing wire segments giving rise to large switching currents across the programmed antifuses that couple the long wire segments together. In some types of antifuses, programmed antifuse reliability is dependent upon maintaining the programming current used to program the antifuse a certain factor greater than the peak switching current flowing through the antifuse during normal operation. The antifuses in these long wire segments therefore should be programmed with proportionately larger programming currents. To increase the programming currents with which these antifuses are programmed, programming current is supplied onto each of the long routing segments from two different programming conductors via two different programming transistors.

摘要翻译： 诸如现场可编程门阵列（见图3）的可编程集成电路具有用于在整个集成电路上传输长距离的信号的几个长的路由线段。 这些长路由线段可以使用编程的反熔丝耦合在一起。 可以使用高驱动输出驱动器来驱动长距离的信号，通过这样的耦合在一起的长路由线段，从而跨越编程的反熔丝产生大的开关电流，将长的电线段耦合在一起。 在某些类型的反熔丝中，编程的反熔丝可靠性取决于在正常操作期间将用于编程反熔丝的编程电流保持在大于流过反熔丝的峰值开关电流的某个因子。 因此，这些长线段中的反熔丝应该按比例更大的编程电流进行编程。 为了增加对这些反熔丝编程的编程电流，通过两个不同的编程晶体管将编程电流提供给来自两个不同编程导体的每个长路由段。

公开(公告)号：US07626418B1

公开(公告)日：2009-12-01

申请号：US11803516

申请日：2007-05-14

申请人： Paige A. Kolze ,  Laurent F. Stadler ,  Patrick C. McCarthy

发明人： Paige A. Kolze ,  Laurent F. Stadler ,  Patrick C. McCarthy

IPC分类号： H03K19/177

CPC分类号： H03K19/17732

摘要： A configurable interface for an integrated circuit is described. The integrated circuit includes a first core, where the first core is an application specific circuit version of a Peripheral Component Interconnect Express (“PCIe”) interface device. First configuration memory cells are associated with the first core, and the first configuration memory cells are for configuring the first core. The first configuration memory cells are programmable responsive to a first portion of a configuration bitstream, and the configuration bitstream is capable of including user-logic information for programming programmable logic of the integrated circuit.

摘要翻译： 描述了用于集成电路的可配置接口。 集成电路包括第一核心，其中第一核心是外围组件互连Express（“PCIe”）接口设备的应用特定电路版本。 第一配置存储器单元与第一核相关联，并且第一配置存储单元用于配置第一核。 响应于配置比特流的第一部分，第一配置存储器单元是可编程的，并且配置比特流能够包括用于编程集成电路的可编程逻辑的用户逻辑信息。