公开(公告)号：US06465314B1

公开(公告)日：2002-10-15

申请号：US09680242

申请日：2000-10-05

申请人： Tongbi Jiang ,  David Y. Kao

发明人： Tongbi Jiang ,  David Y. Kao

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2652

摘要： The invention pertains to semiconductor processing methods of implanting dopants into semiconductor substrates. In one aspect, the invention includes, a semiconductor processing method comprising: a) forming an organic layer over a semiconductive substrate; and b) implanting a conductivity-enhancing dopant through the organic layer and into the semiconductive substrate. In another aspect, the invention includes a semiconductor processing method comprising: a) providing a semiconductive substrate and defining source and drain locations within the semiconductive substrate; b) forming an organic layer over the source and drain locations; c) implanting a conductivity-enhancing dopant through the organic layer and into the source and drain locations to form source and drain implant regions within the source and drain locations, respectively; and d) forming a transistor gate proximate the source and drain implant regions. In another aspect, the invention includes a semiconductor processing method comprising: a) forming a transistor gate over a semiconductive substrate and defining source/drain locations within the semiconductive substrate proximate the transistor gate; b) forming a polyimide layer over the transistor gate and over the source/drain locations; c) depositing photoresist over the polyimide layer; d) patterning the photoresist to form openings over the source/drain locations; and e) implanting a conductivity-enhancing dopant into the openings, through the polyimide layer and into the source/drain locations.

摘要翻译： 本发明涉及将掺杂剂注入到半导体衬底中的半导体处理方法。 一方面，本发明包括半导体处理方法，包括：a）在半导体衬底上形成有机层; 和b）通过有机层注入导电性增强掺杂剂并进入半导体衬底。 在另一方面，本发明包括半导体处理方法，包括：a）提供半导体衬底并限定半导电衬底内的源极和漏极位置; b）在源极和漏极位置上形成有机层; c）通过有机层注入电导率增强掺杂剂并进入源极和漏极位置，以分别在源极和漏极位置内形成源极和漏极注入区域; 以及d）在源极和漏极注入区域附近形成晶体管栅极。 在另一方面，本发明包括一种半导体处理方法，包括：a）在半导体衬底上形成晶体管栅极，并在半导体衬底附近界定晶体管栅极处的源极/漏极位置; b）在晶体管栅极上方和源极/漏极位置上形成聚酰亚胺层; c）在聚酰亚胺层上沉积光致抗蚀剂; d）图案化光致抗蚀剂以在源极/漏极位置上形成开口; 以及e）将导电性增强掺杂剂注入到开口中，通过聚酰亚胺层并进入源极/漏极位置。

公开(公告)号：US6165856A

公开(公告)日：2000-12-26

申请号：US133291

申请日：1998-08-12

申请人： Tongbi Jiang ,  David Y. Kao

发明人： Tongbi Jiang ,  David Y. Kao

IPC分类号： H01L21/265 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/2652

摘要： The invention pertains to semiconductor processing methods of implanting dopants into semiconductor substrates. In one aspect, the invention includes, a semiconductor processing method comprising: a) forming an organic layer over a semiconductive substrate; and b) implanting a conductivity-enhancing dopant through the organic layer and into the semiconductive substrate. In another aspect, the invention includes a semiconductor processing method comprising: a) providing a semiconductive substrate and defining source and drain locations within so the semiconductive substrate; b) forming an organic layer over the source and drain locations; c) implanting a conductivity-enhancing dopant through the organic layer and into the source and drain locations to form source and drain implant regions within the source and drain locations, respectively; and d) forming a transistor gate proximate the source and drain implant regions. In another aspect, the invention includes a semiconductor processing method comprising: a) forming a transistor gate over a semiconductive substrate and defining source/drain locations within the semiconductive substrate proximate the transistor gate; b) forming a polyimide layer over the transistor gate and over the source/drain locations; c) depositing photoresist over the polyimide layer; d) patterning the photoresist to form openings over the source/drain locations; and e) implanting a conductivity-enhancing dopant into the openings, through the polyimide layer and into the source/drain locations.

摘要翻译： 本发明涉及将掺杂剂注入到半导体衬底中的半导体处理方法。 一方面，本发明包括半导体处理方法，包括：a）在半导体衬底上形成有机层; 和b）通过有机层注入导电性增强掺杂剂并进入半导体衬底。 在另一方面，本发明包括一种半导体处理方法，包括：a）提供半导体衬底并限定半导电衬底内的源极和漏极位置; b）在源极和漏极位置上形成有机层; c）通过有机层注入电导率增强掺杂剂并进入源极和漏极位置，以分别在源极和漏极位置内形成源极和漏极注入区域; 以及d）在源极和漏极注入区域附近形成晶体管栅极。 在另一方面，本发明包括一种半导体处理方法，包括：a）在半导体衬底上形成晶体管栅极，并在半导体衬底附近界定晶体管栅极处的源极/漏极位置; b）在晶体管栅极上方和源极/漏极位置上形成聚酰亚胺层; c）在聚酰亚胺层上沉积光致抗蚀剂; d）图案化光致抗蚀剂以在源极/漏极位置上形成开口; 以及e）将导电性增强掺杂剂注入到开口中，通过聚酰亚胺层并进入源极/漏极位置。

公开(公告)号：US06414869B1

公开(公告)日：2002-07-02

申请号：US09614639

申请日：2000-07-12

申请人： David Y. Kao ,  Tongbi Jiang

发明人： David Y. Kao ,  Tongbi Jiang

IPC分类号： G11C506

CPC分类号： G11C5/06 ,  G11C5/04 ,  H05K1/117 ,  H05K1/141 ,  H05K1/148 ,  H05K3/36 ,  H05K3/361 ,  H05K3/366 ,  H05K2201/10159 ,  H05K2201/10189

摘要： A quad in-line memory module (QIMM) includes a circuit board having top and bottom edge connectors and a number of memory devices mounted on each side of the circuit board. Generally, half of the memory devices are electrically connected to the bottom edge's connector and half are electrically connected to the bottom edge's connector. One edge of the QIMM can be connect directly to a computer system's memory bus. The other edge can be connected to operated as a cache memory or a video memory.

摘要翻译： 四行在线存储器模块（QIMM）包括具有顶部和底部边缘连接器以及安装在电路板的每一侧上的多个存储器件的电路板。 通常，一半的存储器件电连接到底部边缘的连接器，一半存储器件电连接到底部边缘的连接器。 QIMM的一个边缘可以直接连接到计算机系统的内存总线。 另一边可连接作为高速缓冲存储器或视频存储器。

公开(公告)号：US06288885B1

公开(公告)日：2001-09-11

申请号：US09388521

申请日：1999-09-02

申请人： Tongbi Jiang ,  David Y. Kao

发明人： Tongbi Jiang ,  David Y. Kao

IPC分类号： H02H322

CPC分类号： H01L23/60 ,  H01L27/0248 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/10253 ,  H05K1/0254 ,  H01L2924/00 ,  H01L2224/05599

摘要： An in its various embodiments is a method and apparatus for electrostatic discharge protection. In one aspect of the present invention, an integrated circuit device capable of providing electrostatic discharge protection for use on a printed circuit board containing a possible source of electrostatic discharge and operational circuitry is provided. The integrated circuit device includes an input coupled to the possible source of electrostatic discharge, an output coupled to the operational circuitry on the printed circuit board, a capacitance structure between the input and the output, and a switch in series with the capacitance structure. The integrated circuit also provides, a method for protecting a printed circuit board from electrostatic discharge by switching the discharge to a capacitance structure for subsequent dissipation into the printed circuit board.

摘要翻译： 其各种实施例中的静电放电保护的方法和装置。 在本发明的一个方面，提供一种能够提供静电放电保护以用于包含可能的静电放电源和操作电路的印刷电路板的集成电路器件。 集成电路器件包括耦合到可能的静电放电源的输入，耦合到印刷电路板上的操作电路的输出，输入和输出之间的电容结构以及与电容结构串联的开关。 集成电路还提供了一种通过将放电切换到电容结构以便随后耗散到印刷电路板中来保护印刷电路板免受静电放电的方法。

公开(公告)号：US6108228A

公开(公告)日：2000-08-22

申请号：US982930

申请日：1997-12-02

申请人： David Y. Kao ,  Tongbi Jiang

发明人： David Y. Kao ,  Tongbi Jiang

IPC分类号： G11C5/00 ,  H05K1/11 ,  H05K1/14 ,  H05K3/36 ,  G11C5/06

CPC分类号： G11C5/06 ,  G11C5/04 ,  H05K1/141 ,  H05K1/117 ,  H05K1/148 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K3/36 ,  H05K3/361 ,  H05K3/366

摘要： A quad in-line memory module (QIMM) includes a circuit board having top and bottom edge connectors and a number of memory devices mounted on each side of the circuit board. Generally, half of the memory devices are electrically connected to the bottom edge's connector and half are electrically connected to the bottom edge's connector. One edge of the QIMM can be connect directly to a computer system's memory bus. The other edge can be connected to operated as a cache memory or a video memory.

公开(公告)号：US06323514B1

公开(公告)日：2001-11-27

申请号：US09348725

申请日：1999-07-06

申请人： David Y. Kao

发明人： David Y. Kao

IPC分类号： H01L29788

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： A floating gate memory device comprises a first conductive floating gate layer which is horizontally oriented and a second conductive floating gate layer which is predominantly vertically oriented. The second layer contacts the first layer to make electrical contact therewith and also defines a recess. A control gate is formed within the recess. Having the control gate formed in the floating gate layer recess increases the capacitive coupling between the floating and control gates thereby improving the electrical properties of the cell and allowing for a reduction in cell size while maintaining

摘要翻译： 浮动栅极存储器件包括水平取向的第一导电浮动栅层和主要垂直取向的第二导电浮栅。 第二层接触第一层以与其电接触并且还限定凹部。 在凹槽内形成控制门。 使形成在浮栅层凹槽中的控制栅极增加了浮置栅极和控制栅极之间的电容耦合，从而提高了电池的电性能并且允许在保持电池尺寸的同时减小电池尺寸

公开(公告)号：US06144068A

公开(公告)日：2000-11-07

申请号：US277030

申请日：1999-03-25

申请人： David Y. Kao ,  Jeff Zhiqiang Wu

发明人： David Y. Kao ,  Jeff Zhiqiang Wu

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/6659 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the substrate; b) forming a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one of the first polarity regions. In another aspect, a transistor device, comprising: a) a transistor gate on a semiconductor substrate; b) a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) a second polarity internal junction region entirely received within one of the first polarity regions. In yet another aspect, A resistor, comprising: a) a gate on a semiconductor substrate, the gate being electrically powered with a gate voltage; b) a first polarity source active region and a first polarity drain active region operatively adjacent the electrically powered gate; c) a second polarity internal junction region entirely received within one of the first polarity regions; and d) a current between the first polarity source active region and the first polarity drain active region, the current being substantially linearly dependent on a voltage at the drain region.

摘要翻译： 一方面，一种在半导体衬底上形成晶体管器件的方法，包括：a）在衬底上形成晶体管栅极; b）形成与晶体管栅极可操作地相邻的第一极性源极有源区和第一极性漏极有源区; 以及c）形成第二极性内部结合区域，所述第二极性内部结合区域完全接收在所述第一极性区域之一内。 在另一方面，一种晶体管器件，包括：a）半导体衬底上的晶体管栅极; b）可操作地邻近晶体管栅极的第一极性源极有源区和第一极性漏极有源区; 以及c）完全接收在所述第一极性区域之一内的第二极性内部连接区域。 在另一方面，一种电阻器，包括：a）半导体衬底上的栅极，栅极由栅极电压供电; b）第一极性源有源区和可操作地邻近电动门的第一极性漏极有源区; c）完全接收在所述第一极性区域之一内的第二极性内部连接区域; 以及d）所述第一极性源极活性区域和所述第一极性漏极有源区域之间的电流，所述电流基本上线性地取决于所述漏极区域处的电压。

公开(公告)号：US6124167A

公开(公告)日：2000-09-26

申请号：US370064

申请日：1999-08-06

申请人： David Y. Kao ,  Li Li

发明人： David Y. Kao ,  Li Li

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/331

CPC分类号： H01L21/28273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

摘要： A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.

公开(公告)号：US07259442B2

公开(公告)日：2007-08-21

申请号：US10920579

申请日：2004-08-17

申请人： David Y. Kao ,  Rongsheng Yang

发明人： David Y. Kao ,  Rongsheng Yang

IPC分类号： H01L29/00

CPC分类号： H01L21/823481 ,  H01L21/763 ,  H01L21/765

摘要： A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

摘要翻译： 提供了选择性掺杂沟槽隔离装置。 优选实施例的沟槽隔离装置包括具有沟槽的半导体衬底。 在沟槽的侧壁上生长薄的氧化物层，并且沟槽被重掺杂的多晶硅填充。 衬底和重掺杂多晶硅之间的功函数差异增加了门控沟槽隔离器件的场阈值电压，使得可以在较高密度集成电路中的相邻有源器件之间形成更小的隔离结构。

公开(公告)号：US07151659B2

公开(公告)日：2006-12-19

申请号：US11038602

申请日：2005-01-18

申请人： David Y. Kao ,  James Peacher

发明人： David Y. Kao ,  James Peacher

IPC分类号： H01G4/005

CPC分类号： H01L29/66181 ,  H01L27/0805 ,  H01L29/94

摘要： In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.