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    Method for manufacturing memory card structure
    2.
    发明申请
    Method for manufacturing memory card structure 审中-公开
    制造存储卡结构的方法

    公开(公告)号：US20070246544A1

    公开(公告)日：2007-10-25

    申请号：US11408481

    申请日：2006-04-20

    申请人： Sheila Yang ,  Hong Chang ,  Dennis Pai ,  Frank Lueng ,  Jay Lin ,  Man Lueng ,  Jerry Lin

    发明人： Sheila Yang ,  Hong Chang ,  Dennis Pai ,  Frank Lueng ,  Jay Lin ,  Man Lueng ,  Jerry Lin

    IPC分类号： G06K19/06

    CPC分类号： G06K19/07743 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014

    摘要： A method for manufacturing memory card structure comprises the steps of. Providing a carry has an upper surface, which is coated with adhered glue, and a lower surface. Providing a substrate has a first surface, which is formed with first electrodes, and a lower surface, a golden finger is formed on the substrate, and is electrically connected to the first electrodes. Providing a passive component is mounted on the first surface of the substrate. Separating the substrate and the carry. Providing a chip is mounted on the first surface of the substrate. Providing a plurality of wires is electrically connected the chip to the first electrodes of the substrate. Providing a compound resin is covered on the chip and wires.

    摘要翻译： 一种用于制造存储卡结构的方法包括以下步骤： 提供携带物具有涂有粘合胶的上表面和下表面。 提供基板具有形成有第一电极的第一表面和下表面，在基板上形成金指，并且电连接到第一电极。 提供无源部件安装在基板的第一表面上。 分离底物和进位。 提供芯片安装在基板的第一表面上。 提供多条导线将芯片电连接到基板的第一电极。 在芯片和电线上覆盖复合树脂。

    A PROCESS METHOD AND STRUCTURE FOR HIGH VOLTAGE MOSFETS
    6.
    发明申请
    A PROCESS METHOD AND STRUCTURE FOR HIGH VOLTAGE MOSFETS 有权
    高压MOSFET的工艺方法和结构

    公开(公告)号：US20140332844A1

    公开(公告)日：2014-11-13

    申请号：US13892191

    申请日：2013-05-10

    申请人： Yongping Ding ,  Lei Zhang ,  Hong Chang ,  Jongoh Kim ,  John Chen

    发明人： Yongping Ding ,  Lei Zhang ,  Hong Chang ,  Jongoh Kim ,  John Chen

    IPC分类号： H01L21/265 ,  H01L29/78 ,  H01L29/739

    CPC分类号： H01L29/78 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7827

    摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

    摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件。 半导体功率器件包括多个沟槽，每个沟槽具有沟槽端点，端点侧壁垂直于沟槽的纵向方向并且从顶表面垂直向下延伸到沟槽底表面。 半导体功率器件还包括设置在沟槽底表面下方的沟槽底部掺杂剂区域和沿端点侧壁设置的侧壁掺杂剂区域，其中侧壁掺杂剂区域沿着沟槽的端点侧壁垂直向下延伸以到达沟槽底部掺杂剂区域，并且 将沟槽底部掺杂剂区域拾取到半导体衬底的顶表面。

    Polysilicon control etch back indicator
    7.
    发明授权
    Polysilicon control etch back indicator 失效
    多晶硅控制回蚀指示器

    公开(公告)号：US08471368B2

    公开(公告)日：2013-06-25

    申请号：US13431551

    申请日：2012-03-27

    申请人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

    发明人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

    IPC分类号： H01L29/06

    CPC分类号： H01L29/7813 ,  H01L22/12 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

    摘要翻译： 本发明公开了一种用于在其上制造电子电路的半导体晶片。 半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部 具有较小的平面沟槽尺寸。

    Shielded gate trench MOSFET device and fabrication
    8.
    发明申请
    Shielded gate trench MOSFET device and fabrication 有权
    屏蔽栅沟槽MOSFET器件和制造

    公开(公告)号：US20110037120A1

    公开(公告)日：2011-02-17

    申请号：US12583191

    申请日：2009-08-14

    申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

    发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

    摘要： A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

    摘要翻译： 半导体器件实施例包括衬底，衬底中的有源栅极沟槽和衬底中的不对称沟槽。 非对称沟槽具有第一沟槽壁和第二沟槽壁，第一沟槽壁衬有具有第一厚度的氧化物，并且第二沟槽壁衬有具有不同于第一厚度的第二厚度的氧化物。 另一半导体器件实施例包括衬底，衬底中的有源栅极沟槽; 以及衬底中的源极多晶硅拾取沟槽。 源多晶硅拾取沟槽包括多晶硅电极，并且多晶硅电极的顶表面在身体区域的底部之下。 另一个半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极，以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。 第二顶栅电极比第二底源电极窄。

    HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES
    9.
    发明申请
    HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES 有权
    高密度TRENCH MOSFET，具有单面罩预定门和接触孔

    公开(公告)号：US20100291744A1

    公开(公告)日：2010-11-18

    申请号：US12847863

    申请日：2010-07-30

    申请人： Yeeheng Lee ,  Hong Chang ,  Tiesheng Li ,  John Chen ,  Anup Bhalla

    发明人： Yeeheng Lee ,  Hong Chang ,  Tiesheng Li ,  John Chen ,  Anup Bhalla

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66621 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/78

    摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.

    摘要翻译： 沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。 在半导体基板的表面上形成硬掩模。 在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。 这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。 接下来将栅极沟槽掩模施加在硬掩模的顶部上。 栅极沟槽掩模覆盖主体接触沟槽并且在栅极沟槽处具有开口。 栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。 第一种导电材料可以填充栅沟以形成栅极。 第二种导电材料可以填充身体接触沟槽以形成身体接触。

    Shallow source MOSFET
    10.
    发明授权
    Shallow source MOSFET 有权
    浅源MOSFET

    公开(公告)号：US07667264B2

    公开(公告)日：2010-02-23

    申请号：US10952231

    申请日：2004-09-27

    申请人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

    发明人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7813 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

    摘要： A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

    摘要翻译： 半导体器件包括漏极，与漏极接触的主体，主体具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中，延伸穿过源和主体的沟槽 并且设置在沟槽中的门具有大致在主体顶表面上方延伸的门顶表面。 一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量 延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。