公开(公告)号：US20080188036A1

公开(公告)日：2008-08-07

申请号：US11672217

申请日：2007-02-07

申请人： Douglas C. La Tulipe ,  Steven E. Steen ,  Anna W. Topol

发明人： Douglas C. La Tulipe ,  Steven E. Steen ,  Anna W. Topol

IPC分类号： H01L21/50

CPC分类号： H01L23/544 ,  H01L21/67092 ,  H01L21/67109 ,  H01L21/67288 ,  H01L21/681 ,  H01L24/94 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2225/06565 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01094 ,  H01L2924/14

摘要： A method, system and program product for bonding two circuitry-including semiconductor substrates, and a related stage, are disclosed. In one embodiment, a method of bonding two circuitry-including substrates includes: providing a first stage for holding a first circuitry-including substrate and a second stage for holding a second circuitry-including substrate; identifying an alignment mark on each substrate; determining a location and a topography of each alignment mark using laser diffraction; creating an alignment model for each substrate based on the location and topography the alignment mark thereon; and bonding the first and second circuitry-including substrates together while aligning the first and second substrate based on the alignment model.

摘要翻译： 公开了一种用于键合包含两个电路的半导体衬底和相关阶段的方法，系统和程序产品。 在一个实施例中，一种键合包含两个电路的衬底的方法包括：提供用于保持包含第一电路的衬底的第一级和用于保持包括第二电路的衬底的第二级; 识别每个基板上的对准标记; 使用激光衍射确定每个对准标记的位置和形貌; 基于位置创建每个基板的对准模型，并在其上形成对准标记; 以及基于所述对准模型，将所述第一和第二基于电路的基板接合在一起，同时对准所述第一和第二基板。

公开(公告)号：US20080217782A1

公开(公告)日：2008-09-11

申请号：US11682638

申请日：2007-03-06

申请人： David J. Frank ,  Douglas C. La Tulipe ,  Leathen Shi ,  Steven E. Steen ,  Anna W. Topol

发明人： David J. Frank ,  Douglas C. La Tulipe ,  Leathen Shi ,  Steven E. Steen ,  Anna W. Topol

IPC分类号： H01L23/52 ,  H01L21/30 ,  H01L21/4763

CPC分类号： H01L27/1203 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method which is intended to facilitate and/or simplify the process of fabricating interlayer vias by selective modification of the FEOL film stack on a transfer wafer is provided. Specifically, the present invention provides a method in which two dimensional devices are prepared for subsequent integration in a third dimension at the transition between normal FEOL processes by using an existing interlayer contact mask to define regions in which layers of undesirable dielectrics and metal are selectively removed and refilled with a middle-of-the-line (MOL) compatible dielectric film. As presented, the inventive method is compatible with standard FEOL/MOL integration schemes, and it guarantees a homogeneous dielectric film stack specifically in areas where interlayer contacts are to be formed, thus allowing the option of a straightforward integration path, if desired.

摘要翻译： 提供了一种旨在通过在转移晶片上选择性修改FEOL膜堆来促进和/或简化制造层间通孔的方法的方法。 具体而言，本发明提供了一种方法，其中通过使用现有的层间接触掩模来限定在不期望的电介质层和金属层被选择性去除的区域，准备二维器件用于随后在正常FEOL工艺之间的过渡处的第三维中的集成 并重新填充中间线（MOL）兼容的电介质膜。 如所述的，本发明的方法与标准的FEOL / MOL集成方案兼容，并且其保证了在要形成层间接触的区域中特别是均匀的电介质膜堆叠，因此如果需要，可以选择直接的积分路径。

公开(公告)号：US20080206977A1

公开(公告)日：2008-08-28

申请号：US11677598

申请日：2007-02-22

申请人： David J. Frank ,  Douglas C. La Tulipe ,  Steven E. Steen ,  Anna W. Topol

发明人： David J. Frank ,  Douglas C. La Tulipe ,  Steven E. Steen ,  Anna W. Topol

IPC分类号： H01L21/44

CPC分类号： H01L29/66477 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.

摘要翻译： 公开了向晶体管和相关晶体管布线的方法。 在一个实施例中，该方法包括一种向晶体管形成布线的方法，所述方法包括：使用作为预期布局的镜像的掩模在绝缘体上半导体（SOI）衬底上形成晶体管，所述形成包括形成 栅极和源极/漏极区域，所述SOI衬底包括绝缘体上半导体（SOI）层，掩埋绝缘体层和硅衬底; 在所述晶体管上形成介电层; 将介电层粘合到另一基底上; 将硅衬底从SOI衬底移除到掩埋绝缘体层; 从栅极的沟道侧形成与源极/漏极区域和栅极中的每一个的接触; 以及形成至少一条布线到栅极通道侧上的触点。

公开(公告)号：US20080203137A1

公开(公告)日：2008-08-28

申请号：US11680183

申请日：2007-02-28

申请人： Douglas C. La Tulipe ,  Steven E. Steen ,  Anna W. Topol

发明人： Douglas C. La Tulipe ,  Steven E. Steen ,  Anna W. Topol

IPC分类号： B23K31/12

CPC分类号： B23K31/12 ,  B23K2101/40

摘要： Bonding methods and a bonding system including monitoring are disclosed. In one embodiment, a method of monitoring bonding a first and second substrate includes: providing a plurality of piezoelectric sensors to a substrate mounting stage of a substrate bonding system; and monitoring a force change measured by the plurality of piezoelectric sensors induced by a bond front between the first and second substrate during bonding. This method allows real time monitoring of the bonding quality and adjustment of the bonding process parameters.

摘要翻译： 公开了粘合方法和包括监测在内的粘合系统。 在一个实施例中，一种监测接合第一和第二衬底的方法包括：向衬底接合系统的衬底安装级提供多个压电传感器; 以及监测由接合期间由所述第一和第二基板之间的接合前部引起的所述多个压电传感器测量的力变化。 该方法允许实时监测接合质量和调整接合工艺参数。

公开(公告)号：US20080171423A1

公开(公告)日：2008-07-17

申请号：US11622543

申请日：2007-01-12

申请人： Meikei Ieong ,  Douglas C. La Tulipe ,  Leathen Shi ,  Anna W. Topol ,  James Vichiconti ,  Albert M. Young

发明人： Meikei Ieong ,  Douglas C. La Tulipe ,  Leathen Shi ,  Anna W. Topol ,  James Vichiconti ,  Albert M. Young

IPC分类号： H01L21/20

CPC分类号： H01L21/02658 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

摘要： A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.

摘要翻译： 提供了一种制造应变绝缘体上半导体（SSOI）结构的成本有效和简单的方法，其避免了外延生长和随后的晶片接合处理步骤。 根据本发明，使用应变记忆技术在SOI衬底上产生应变半导体区域。 形成在应变半导体区域上的晶体管具有更高的载流子迁移率，因为Si区域已经变形。 本发明的方法包括（i）离子注入以产生薄的非晶化层，（ii）在非晶化层上沉积高应力膜，（iii）热退火以使非晶化层重结晶，和（iv）去除应力 电影。 由于在再结晶过程中SOI衬底处于应力状态，所以最终的半导体层也将受到应力。 应力的量和应力的极性（拉伸或压缩）可以通过应力膜的类型和厚度来控制。

公开(公告)号：US07241681B2

公开(公告)日：2007-07-10

申请号：US11330834

申请日：2006-01-12

申请人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

发明人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1036 ,  Y10T428/12576 ,  Y10T428/12806 ,  Y10T428/265 ,  Y10T428/31678

摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

摘要翻译： 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

公开(公告)号：US07052621B2

公开(公告)日：2006-05-30

申请号：US10461090

申请日：2003-06-13

申请人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

发明人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

IPC分类号： C23F1/00

CPC分类号： H01L21/76832 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1036 ,  Y10T428/12576 ,  Y10T428/12806 ,  Y10T428/265 ,  Y10T428/31678

摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

摘要翻译： 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

公开(公告)号：US20130187229A1

公开(公告)日：2013-07-25

申请号：US13354363

申请日：2012-01-20

申请人： KANGGUO CHENG ,  Bruce B. Doris ,  Ali Khakifirooz ,  Douglas C. La Tulipe

发明人： KANGGUO CHENG ,  Bruce B. Doris ,  Ali Khakifirooz ,  Douglas C. La Tulipe

IPC分类号： H01L29/772 ,  G06F9/45 ,  H01L21/336

CPC分类号： H01L29/78603 ,  H01L29/0847 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78654

摘要： A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions.

公开(公告)号：US07091612B2

公开(公告)日：2006-08-15

申请号：US10684952

申请日：2003-10-14

申请人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas C. La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

发明人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas C. La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

IPC分类号： H01L23/12 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

公开(公告)号：US07125792B2

公开(公告)日：2006-10-24

申请号：US10685055

申请日：2003-10-14

申请人： Kaushik Kumar ,  Douglas C. La Tulipe ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht

发明人： Kaushik Kumar ,  Douglas C. La Tulipe ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht

IPC分类号： H01L21/4763

CPC分类号： H01L21/76835 ,  H01J37/32862 ,  H01L21/02046 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/76811

摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

摘要翻译： 一种双镶嵌结构及其制造方法。 绝缘层包括第一介电材料和第二电介质材料，第二电介质材料不同于第一电介质材料。 具有第一图案的第一导电区域形成在第一电介质材料中，并且具有第二图案的第二导电区域形成在第二电介质材料中，第二图案不同于第一图案。 第一电介质材料和第二电介质材料之一包括有机材料，而另一介电材料包括无机材料。 第一和第二介电材料之一是可蚀刻的对另一种介电材料的选择性。 还公开了当晶片保持在室内时清洁半导体晶片处理室的方法。