公开(公告)号：US20070296053A1

公开(公告)日：2007-12-27

申请号：US11757505

申请日：2007-06-04

申请人： Eiji Hasunuma ,  Yoshinori Tanaka ,  Keizo Kawakita

发明人： Eiji Hasunuma ,  Yoshinori Tanaka ,  Keizo Kawakita

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L21/3247 ,  H01L29/0657 ,  H01L29/1037 ,  H01L29/66628

摘要： A method of forming a semiconductor device is provided. A device isolation region is formed in a semiconductor substrate, thereby defining a device region in the semiconductor substrate. The device region has a flat main surface. The flat main surface is deformed into a round surface, thereby forming a surface-rounded device region. The surface-rounded device region includes a side portion that is adjacent to a boundary with the device isolation region. The surface-rounded device region has a convex shape in vertical cross section. An epitaxial layer is selectively formed on the round surface of the surface-rounded device region. A first ion-implantation process is carried out for introducing an impurity into at least one of the epitaxial layer and the surface-rounded device region.

摘要翻译： 提供一种形成半导体器件的方法。 在半导体衬底中形成器件隔离区，从而在半导体衬底中限定器件区域。 器件区域具有平坦的主表面。 平面主表面变形为圆形表面，从而形成表面圆整装置区域。 表面圆形装置区域包括与装置隔离区域的边界相邻的侧部。 表面圆形装置区域在垂直截面上具有凸形形状。 在表面圆整装置区域的圆形表面上选择性地形成外延层。 进行第一离子注入工艺以将杂质引入到外延层和表面圆形装置区域中的至少一个中。

公开(公告)号：US20070002601A1

公开(公告)日：2007-01-04

申请号：US11472336

申请日：2006-06-22

申请人： Eiji Hasunuma ,  Keizo Kawakita ,  Yoshinori Tanaka ,  Noriaki Mikasa

发明人： Eiji Hasunuma ,  Keizo Kawakita ,  Yoshinori Tanaka ,  Noriaki Mikasa

IPC分类号： G11C5/02

CPC分类号： G11C7/18 ,  G11C11/4097

摘要： Improved open bit line architecture is disclosed, comprising two types of memory cell groups, which are different in size from each other. Normal memory mats are arranged in a predetermined direction and each comprises smaller sized memory cells such as 6F2 cells. Two end memory mats are arranged to sandwich the normal memory mats in the predetermined direction and comprises larger sized memory cells such as 8F2 cells. With the architecture, some advantages of folded bit line structure are introduced into open bit line structure.

摘要翻译： 公开了改进的开放位线架构，其包括彼此尺寸不同的两种类型的存储单元组。 正常存储器垫按预定方向布置，并且每个都包含较小尺寸的存储单元，例如6F 2个单元。 布置两个末端存储垫以沿着预定方向夹住正常的存储垫，并且包括较大尺寸的存储单元，例如8F 2个单元。 利用架构，将折叠位线结构的一些优点引入开放位线结构。

公开(公告)号：US06596582B2

公开(公告)日：2003-07-22

申请号：US10271580

申请日：2002-10-17

申请人： Yoshitaka Fujiishi ,  Yoshinori Tanaka ,  Eiji Hasunuma

发明人： Yoshitaka Fujiishi ,  Yoshinori Tanaka ,  Eiji Hasunuma

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L28/84 ,  H01L28/91

摘要： There can be provided a semiconductor device having a rough surface to provide an increased capacitance of a capacitor and enhanced prevention of short-circuit between capacitors, and a method of manufacturing the same. The semiconductor device includes a plug interconnection penetrating an insulating film and connected to an underlying wiring, and a storage node having a lower portion overlying the insulating film and free of a rough surface, and connected to the plug interconnection, and an upper portion overlying the lower portion of the storage node without covering a side surface of the lower portion of the storage node, and having a rough surface.

摘要翻译： 可以提供具有粗糙表面以提供电容器的增加的电容并增强电容器之间短路的防止的半导体器件及其制造方法。 半导体器件包括穿透绝缘膜并连接到下面的布线的插头互连，以及具有覆盖绝缘膜并且没有粗糙表面的下部并且连接到插头互连的下部的存储节点，以及覆盖 存储节点的下部，而不覆盖存储节点的下部的侧表面，并且具有粗糙表面。

公开(公告)号：US20070241380A1

公开(公告)日：2007-10-18

申请号：US11686885

申请日：2007-03-15

申请人： Eiji Hasunuma

发明人： Eiji Hasunuma

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： a semiconductor storage device is provided with a plurality of active regions formed in the shape of a band in a semiconductor substrate; a plurality of word lines arranged at equal intervals so as to intersect the active regions; a plurality of cell contacts that includes first cell contacts formed in the active regions in the center portions in the longitudinal direction thereof, and second cell contacts formed at each end portion at both ends in the longitudinal direction; bit line contacts formed on the first cell contacts; bit lines wired so as to pass over the bit line contacts; storage node contacts formed on the second cell contacts; storage node contact pads formed on the storage node contacts; and storage capacitors formed on the storage node contact pads. The center positions of the storage node contacts are offset in a prescribed direction from the center positions of the second cell contacts. The center positions of the storage node contact pads are offset in a prescribed direction from the center positions of the storage node contacts.

摘要翻译： 半导体存储装置设置有形成为半导体衬底中的带状形状的多个有源区域; 多个字线，以相等的间隔布置成与有源区相交; 多个单元触点，其包括形成在其纵向方向上的中心部分中的有源区域中的第一单元触点和形成在纵向两端的每个端部处的第二单元触点; 在第一单元触点上形成的位线触点; 位线被布线以便通过位线触点; 形成在第二电池触头上的存储节点触点; 存储节点接触垫形成在存储节点上; 以及形成在存储节点接触垫上的存储电容器。 存储节点触点的中心位置从与第二单元触点的中心位置规定的方向偏移。 存储节点接触垫的中心位置从与存储节点接触件的中心位置的规定方向偏移。

公开(公告)号：US06504192B2

公开(公告)日：2003-01-07

申请号：US09888389

申请日：2001-06-26

申请人： Eiji Hasunuma

发明人： Eiji Hasunuma

IPC分类号： H01L2976

CPC分类号： H01L29/4983 ,  H01L21/31116 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： With respect to a desired gate electrode (A) and dummy gate electrodes (B, C), side wall spacers (3a, 3b, 3c) of the respective gate electrodes are formed by dry etching such as an RIE method, and the etching characteristic at the time of formation of the side wall spacer is utilized so that the side wall spacer width of the desired gate electrode is controlled by adjusting gap differences between the gate electrodes by properly arranging the dummy electrode; and thus, it is possible to obtain desired transistor characteristics.

摘要翻译： 对于期望的栅电极（A）和虚拟栅电极（B，C），通过诸如RIE法的干蚀刻形成各个栅电极的侧壁间隔物（3a，3b，3c），并且蚀刻特性 在形成侧壁间隔物时，通过适当地布置虚拟电极，通过调节栅电极之间的间隙来控制所需栅电极的侧壁间隔物的宽度; 因此，可以获得期望的晶体管特性。

公开(公告)号：US07723184B2

公开(公告)日：2010-05-25

申请号：US11984794

申请日：2007-11-21

申请人： Eiji Hasunuma

发明人： Eiji Hasunuma

IPC分类号： H01L21/336

CPC分类号： H01L29/42368 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/66666 ,  H01L29/7827

摘要： A semiconductor device is provided which is suitable for a DRAM with word lines and configured to have a trench gate transistor and suppress an increase in the capacitance of a word line without affecting the transistor characteristics. The semiconductor device includes a trench gate transistor which is provided with: a trench which is provided with vertical sides and is formed in a semiconductor substrate; a gate electrode which is formed inside the trench via a gate dielectric film; and a source and a drain which are provided at the semiconductor substrate in the vicinity of the gate electrode via the gate dielectric film, wherein at least one of the thickness of the gate dielectric film in a region contacting the source and the thickness of the gate dielectric film in a region contacting the drain are larger than the thickness of the gate dielectric film formed inside the trench.

摘要翻译： 提供一种适用于具有字线的DRAM并配置为具有沟槽栅极晶体管并且抑制字线的电容增加而不影响晶体管特性的半导体器件。 半导体器件包括沟槽栅极晶体管，其设置有：设置有垂直侧并形成在半导体衬底中的沟槽; 栅电极，其经由栅极电介质膜形成在沟槽内; 以及源极和漏极，其经由栅极电介质膜设置在所述栅极电极附近的所述半导体衬底处，其中所述栅极电介质膜在与所述源极接触的区域中的厚度和所述栅极的厚度中的至少一个 在与漏极接触的区域中的介电膜大于形成在沟槽内部的栅极电介质膜的厚度。

公开(公告)号：US08786000B2

公开(公告)日：2014-07-22

申请号：US13338909

申请日：2011-12-28

申请人： Eiji Hasunuma

发明人： Eiji Hasunuma

IPC分类号： H01L29/92

CPC分类号： H01L27/0207 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/92

摘要： A method of manufacturing a semiconductor device includes: forming a core insulating film that includes first openings, on a semiconductor substrate; forming cylindrical lower electrodes that cover sides of the first openings with a conductive film; forming a support film that covers at least an upper surface of the core insulating film between the lower electrodes; forming a mask film in which an outside of a region where at least the lower electrodes are formed is removed, by using the support film; and performing isotropic etching on the core insulating film so as to leave the core insulating film at a part of an area between the lower electrodes, after the mask film is formed.

摘要翻译： 一种制造半导体器件的方法包括：在半导体衬底上形成包括第一开口的芯绝缘膜; 用导电膜形成覆盖第一开口侧面的圆筒形下电极; 形成覆盖所述下部电极之间的所述芯绝缘膜的至少上表面的支撑膜; 形成掩模膜，其中至少形成下部电极的区域的外部被去除，通过使用支撑膜; 并且在形成掩模膜之后，在芯绝缘膜上进行各向同性蚀刻，以将芯绝缘膜留在下电极之间的一部分区域。

公开(公告)号：US08093724B2

公开(公告)日：2012-01-10

申请号：US11686885

申请日：2007-03-15

申请人： Eiji Hasunuma

发明人： Eiji Hasunuma

IPC分类号： H01L29/40

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： a semiconductor storage device is provided with a plurality of active regions formed in the shape of a band in a semiconductor substrate; a plurality of word lines arranged at equal intervals so as to intersect the active regions; a plurality of cell contacts that includes first cell contacts formed in the active regions in the center portions in the longitudinal direction thereof, and second cell contacts formed at each end portion at both ends in the longitudinal direction; bit line contacts formed on the first cell contacts; bit lines wired so as to pass over the bit line contacts; storage node contacts formed on the second cell contacts; storage node contact pads formed on the storage node contacts; and storage capacitors formed on the storage node contact pads. The center positions of the storage node contacts are offset in a prescribed direction from the center positions of the second cell contacts. The center positions of the storage node contact pads are offset in a prescribed direction from the center positions of the storage node contacts.

摘要翻译： 半导体存储装置设置有形成为半导体衬底中的带状形状的多个有源区域; 多个字线，以相等的间隔布置成与有源区相交; 多个单元触点，其包括形成在其纵向方向上的中心部分中的有源区域中的第一单元触点和形成在纵向两端的每个端部处的第二单元触点; 在第一单元触点上形成的位线触点; 位线被布线以便通过位线触点; 形成在第二电池触头上的存储节点触点; 存储节点接触垫形成在存储节点上; 以及形成在存储节点接触垫上的存储电容器。 存储节点触点的中心位置从与第二单元触点的中心位置规定的方向偏移。 存储节点接触垫的中心位置从与存储节点接触件的中心位置的规定方向偏移。

公开(公告)号：US20080121990A1

公开(公告)日：2008-05-29

申请号：US11984794

申请日：2007-11-21

申请人： Eiji Hasunuma

发明人： Eiji Hasunuma

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42368 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/66666 ,  H01L29/7827

摘要： A semiconductor device is provided which is suitable for a DRAM with word lines and configured to have a trench gate transistor and suppress an increase in the capacitance of a word line without affecting the transistor characteristics. The semiconductor device includes a trench gate transistor which is provided with: a trench which is provided with vertical sides and is formed in a semiconductor substrate; a gate electrode which is formed inside the trench via a gate dielectric film; and a source and a drain which are provided at the semiconductor substrate in the vicinity of the gate electrode via the gate dielectric film, wherein at least one of the thickness of the gate dielectric film in a region contacting the source and the thickness of the gate dielectric film in a region contacting the drain are larger than the thickness of the gate dielectric film formed inside the trench.

摘要翻译： 提供一种适用于具有字线的DRAM并配置为具有沟槽栅极晶体管并且抑制字线的电容增加而不影响晶体管特性的半导体器件。 半导体器件包括沟槽栅极晶体管，其设置有：设置有垂直侧并形成在半导体衬底中的沟槽; 栅电极，其经由栅极电介质膜形成在沟槽内; 以及源极和漏极，其经由栅极电介质膜设置在所述栅极电极附近的所述半导体衬底处，其中所述栅极电介质膜在与所述源极接触的区域中的厚度和所述栅极的厚度中的至少一个 在与漏极接触的区域中的介电膜大于形成在沟槽内部的栅极电介质膜的厚度。

公开(公告)号：US06765251B2

公开(公告)日：2004-07-20

申请号：US09227935

申请日：1999-01-11

申请人： Eiji Hasunuma ,  Hideki Genjo ,  Shigeru Shiratake ,  Atsushi Hachisuka ,  Koji Taniguchi

发明人： Eiji Hasunuma ,  Hideki Genjo ,  Shigeru Shiratake ,  Atsushi Hachisuka ,  Koji Taniguchi

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L21/28568 ,  H01L21/76814 ,  H01L21/76831 ,  H01L27/10808

摘要： In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.

摘要翻译： 在半导体装置中，为了满足半导体装置的小型化使接触孔的直径减小的要求，没有被氢氟酸腐蚀的抗HF侧壁膜由隔离膜形成，例如 氮化物膜设置在接触孔的侧壁上。 此外，在接触孔下端附近的硅衬底1中设置有连接到一对n型源极/漏极区域中的一个和到达p型隔离区域的第一杂质区域的第二杂质区域。 由于这种结构，可以根据小型半导体器件的需要防止用于形成互连层的直径的膨胀，因此可以提供稳定半导体器件的操作特性的半导体器件及其制造方法。