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    Copper interconnect structure and its formation
    3.
    发明授权
    Copper interconnect structure and its formation 有权
    铜互连结构及其形成

    公开(公告)号：US08969197B2

    公开(公告)日：2015-03-03

    申请号：US13475526

    申请日：2012-05-18

    申请人： Daniel C. Edelstein ,  Takeshi Nogami ,  Christopher Parks ,  Tsong-Lin Tai

    发明人： Daniel C. Edelstein ,  Takeshi Nogami ,  Christopher Parks ,  Tsong-Lin Tai

    IPC分类号： H01L21/44

    CPC分类号： H01L23/53238 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/522 ,  H01L23/53209 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/76 ,  H01L24/82 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.

    摘要翻译： 具有改进的电迁移阻力的结构及其制造方法。 具有改进的电迁移电阻的结构包括具有双层盖和介电覆盖层的体互连。 双层帽包括底部金属部分和顶部金属氧化物部分。 优选地，金属氧化物部分是MnO或MnSiO，金属部分是Mn或CuMn。 通过用杂质（在优选实施例中为Mn）掺杂互连，然后在互连的顶部处产生晶格缺陷来产生该结构。 这些缺陷驱使增加的杂质向互连顶表面迁移。 当形成电介质盖层时，一部分与分离的杂质反应，从而在互连上形成双层盖。 Cu表面的晶格缺陷可以通过等离子体处理，离子注入，压缩薄膜或其他方式产生。

    Method of making a copper interconnect having a barrier liner of multiple metal layers
    4.
    发明授权
    Method of making a copper interconnect having a barrier liner of multiple metal layers 有权
    制造具有多个金属层的阻挡衬里的铜互连的方法

    公开(公告)号：US08841212B2

    公开(公告)日：2014-09-23

    申请号：US13609668

    申请日：2012-09-11

    申请人： Takeshi Nogami ,  Thomas M. Shaw ,  Andrew H. Simon ,  Jean E. Wynne ,  Chih-Chao Yang

    发明人： Takeshi Nogami ,  Thomas M. Shaw ,  Andrew H. Simon ,  Jean E. Wynne ,  Chih-Chao Yang

    IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/532

    CPC分类号： H01L23/53238 ,  H01L21/76844 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.

    摘要翻译： 一种方法图形为多级集成电路结构的低K绝缘体层中的至少一个开口，使得铜导体在开口的底部露出。 该方法然后在第一室中用第一钽氮化物层排列开口的侧壁和底部，并在第一室中的第一氮化钽层上形成钽层。 接下来，在第一室中进行对开口的溅射蚀刻，以使开口底部的导体露出。 在第一室中再次在导体，钽层和第一氮化钽层上形成第二钽氮化物层。 在形成第二钽氮化物层之后，本文的方法在第二不同室中在第二氮化钽层上形成包含铂族金属的闪蒸层。

    INTERCONNECT WITH TITANIUM-OXIDE DIFFUSION BARRIER
    5.
    发明申请
    INTERCONNECT WITH TITANIUM-OXIDE DIFFUSION BARRIER 审中-公开
    与氧化钛扩散障碍物相互连接

    公开(公告)号：US20130307153A1

    公开(公告)日：2013-11-21

    申请号：US13474944

    申请日：2012-05-18

    申请人： Daniel C. Edelstein ,  Takeshi Nogami

    发明人： Daniel C. Edelstein ,  Takeshi Nogami

    IPC分类号： H01L23/482

    CPC分类号： H01L23/53209 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure located on a semiconductor substrate within a dielectric material positioned atop the semiconductor substrate is provided having an opening within the dielectric material, the opening includes an electrically conductive material extending from the bottom to the top, and contacting the sidewall; a first layer located on the sidewall of the opening, the first layer is made from a material including titanium oxide or titanium silicon oxide; a second layer located between the first layer and the electrically conductive material, the second layer is made from a material selected from the group TiXOb, TiXSiaOb, XOb, and XSiaOb, X is Mn, Al, Sn, In, or Zr; and a third layer located along a top surface of the electrically conductive material, the third layer is made from a material selected from the group TiXOb, TiXSiaOb, XOb, and XSiaOb, X is Mn, Al, Sn, In, or Zr.

    摘要翻译： 设置在位于半导体衬底顶部的介电材料内的半导体衬底上的互连结构，其具有在电介质材料内的开口，该开口包括从底部延伸到顶部并与侧壁接触的导电材料; 位于所述开口的侧壁上的第一层，所述第一层由包括氧化钛或氧化钛钛的材料制成; 位于第一层和导电材料之间的第二层，第二层由选自TiXOb，TiXSiaOb，XOb和XSiaOb的材料制成，X是Mn，Al，Sn，In或Zr; 以及沿着导电材料的顶表面设置的第三层，第三层由选自TiXOb，TiXSiaOb，XOb和XSiaOb的材料制成，X是Mn，Al，Sn，In或Zr。

    SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING ENHANCED PERFORMANCE AND RELIABILITY
    7.
    发明申请
    SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING ENHANCED PERFORMANCE AND RELIABILITY 有权
    具有增强性能和可靠性的半导体互连结构

    公开(公告)号：US20130075908A1

    公开(公告)日：2013-03-28

    申请号：US13246904

    申请日：2011-09-28

    申请人： Cyril Cabral, JR. ,  Geraud Jean-Michel Dubois ,  Daniel C. Edelstein ,  Takeshi Nogami ,  Daniel P. Sanders

    发明人： Cyril Cabral, JR. ,  Geraud Jean-Michel Dubois ,  Daniel C. Edelstein ,  Takeshi Nogami ,  Daniel P. Sanders

    IPC分类号： H01L23/482 ,  H01L21/768

    CPC分类号： H01L23/5226 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

    摘要翻译： 公开了一种用于制造具有增强的性能和可靠性的互连结构的互连结构和方法，通过最小化氧侵入种子层和互连结构的电镀铜层。 形成电介质层中的至少一个开口。 形成设置在电介质层上的牺牲氧化层。 牺牲氧化层使氧侵入种子层和互连结构的电镀铜层最小化。 形成设置在牺牲氧化层上的阻挡金属层。 形成设置在阻挡金属层上的籽晶层。 形成设置在种子层上的电镀铜层。 形成平坦化表面，其中除去部分牺牲氧化层，阻挡金属层，种子层和电镀铜层。 此外，形成设置在平坦化表面上的覆盖层。

    Formation of air gap with protection of metal lines
    8.
    发明授权
    Formation of air gap with protection of metal lines 失效
    形成气隙，保护金属线

    公开(公告)号：US08399350B2

    公开(公告)日：2013-03-19

    申请号：US12700792

    申请日：2010-02-05

    申请人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L21/4763

    CPC分类号： H01L24/80 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

    摘要： Method for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer, and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask exposes a surface of only the second portion of the cap layer which has the greater height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer. Material can be removed from the dielectric layer where exposed to the etchant.

    摘要翻译： 一种在其电介质层中具有气隙的微电子元件的制造方法。 可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并延伸第二高度 高于介电层表面的高度，第二高度大于第一高度。 在形成盖层之后，可以在盖层之上形成掩模。 掩模仅暴露具有较大高度的盖层的第二部分的表面。 随后，蚀刻剂可以被引导到盖层的第一和第二部分。 材料可以从暴露于蚀刻剂的介电层去除。

    CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS
    10.
    发明申请
    CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS 有权
    创造不同深度的VIAS和TRENCHES

    公开(公告)号：US20120171859A1

    公开(公告)日：2012-07-05

    申请号：US13415164

    申请日：2012-03-08

    申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    IPC分类号： H01L21/768

    CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

    摘要翻译： 本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。 该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。 还提供了由此制成的半导体结构。