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公开(公告)号:US07907090B2
公开(公告)日:2011-03-15
申请号:US11759523
申请日:2007-06-07
申请人: Eli Bershadsky , Marina Kravchik , Reuven Katraro , David Ben-Bassat , Dani Alon
发明人: Eli Bershadsky , Marina Kravchik , Reuven Katraro , David Ben-Bassat , Dani Alon
IPC分类号: H01Q1/24
CPC分类号: C04B35/47 , C04B2235/3208 , C04B2235/3215 , C04B2235/3229 , C04B2235/3236 , C04B2235/3244 , C04B2235/3248 , C04B2235/3262 , C04B2235/3284 , C04B2235/3298 , C04B2235/349 , C04B2235/36 , C04B2235/656 , C04B2235/72
摘要: A dielectric ceramic composition has a dielectric constant, K, of at least 200 and a dielectric loss, DF, of 0.0006 or less at 1 MHz. The dielectric ceramic composition may be formed by sintering by firing in air without a controlled atmosphere. The dielectric ceramic composition may have a major component of 92.49 to 97.5 wt. % containing 60.15 to 68.2 wt. % strontium titanate, 11.02 to 23.59 wt. % calcium titanate and 7.11 to 21.32 wt. % barium titanate; and a minor component of 2.50 to 7.51 wt. % containing 1.18 to 3.55 wt. % calcium zirconate, 0.50 to 1.54 wt. % bismuth trioxide, 0.2 to 0.59 wt. % zirconia, 0.02 to 0.07 wt. % manganese dioxide, 0.12 to 0.35 wt. % zinc oxide, 0.12 to 0.35 wt. % lead-free glass frit, 0.24 to 0.71 wt. % kaolin clay and 0.12 to 0.35 wt. % cerium oxide. UHF antennas and monolithic ceramic components may use the dielectric ceramic composition.
摘要翻译: 介电陶瓷组合物的介电常数K至少为200,介电损耗DF在1MHz时为0.0006以下。 电介质陶瓷组合物可以通过在没有受控气氛的空气中烧制而烧结而形成。 介电陶瓷组合物可以具有92.49至97.5重量%的主要组分。 %含有60.15〜68.2重量% %钛酸锶,11.02〜23.59重量% 钛酸钙和7.11〜21.32重量% %钛酸钡; 和2.50〜7.51重量%的次要组分。 %含有1.18〜3.55重量% 锆酸钙,0.50〜1.54重量% 三氧化二铋,0.2〜0.59重量% %氧化锆,0.02〜0.07重量% %二氧化锰,0.12〜0.35wt。 %氧化锌,0.12〜0.35重量% %无铅玻璃料,0.24至0.71wt。 %的高岭土和0.12〜0.35wt。 %的氧化铈。 UHF天线和单片陶瓷组件可以使用介电陶瓷组合物。
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公开(公告)号:US20120300363A1
公开(公告)日:2012-11-29
申请号:US13567317
申请日:2012-08-06
IPC分类号: H01G4/12
CPC分类号: H01G9/15 , H01G9/0032 , H01G9/052 , H01G9/055 , Y10T29/435
摘要: A bulk capacitor includes a first electrode formed of a metal foil and a semi-conductive porous ceramic body formed on the metal foil. A dielectric layer is formed on the porous ceramic body for example by oxidation. A conductive medium is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.
摘要翻译: 大容量电容器包括由金属箔形成的第一电极和形成在金属箔上的半导体多孔陶瓷体。 例如通过氧化在多孔陶瓷体上形成电介质层。 导电介质沉积在填充多孔陶瓷体的孔隙并形成第二电极的多孔陶瓷体上。 然后电容器可以用各种层封装,并且可以包括常规的电终端。 制造大容量电容器的方法包括在由金属箔形成的第一电极上形成导电多孔陶瓷体,氧化以形成电介质层,并用导电介质填充多孔体以形成第二电极。 也可以在金属箔和多孔陶瓷体之间设置薄的半导体陶瓷层。
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公开(公告)号:US08238076B2
公开(公告)日:2012-08-07
申请号:US12553508
申请日:2009-09-03
IPC分类号: H01G4/00
CPC分类号: H01G9/15 , H01G9/0032 , H01G9/052 , H01G9/055 , Y10T29/435
摘要: A bulk capacitor includes a first electrode formed of a metal foil and a semi-conductive porous ceramic body formed on the metal foil. A dielectric layer is formed on the porous ceramic body for example by oxidation. A conductive medium is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.
摘要翻译: 大容量电容器包括由金属箔形成的第一电极和形成在金属箔上的半导体多孔陶瓷体。 例如通过氧化在多孔陶瓷体上形成电介质层。 导电介质沉积在填充多孔陶瓷体的孔隙并形成第二电极的多孔陶瓷体上。 然后电容器可以用各种层封装,并且可以包括常规的电终端。 制造大容量电容器的方法包括在由金属箔形成的第一电极上形成导电多孔陶瓷体,氧化以形成电介质层,并用导电介质填充多孔体以形成第二电极。 也可以在金属箔和多孔陶瓷体之间设置薄的半导体陶瓷层。
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公开(公告)号:US20100073846A1
公开(公告)日:2010-03-25
申请号:US12553508
申请日:2009-09-03
CPC分类号: H01G9/15 , H01G9/0032 , H01G9/052 , H01G9/055 , Y10T29/435
摘要: A bulk capacitor includes a first electrode formed of a metal foil and a semi-conductive porous ceramic body formed on the metal foil. A dielectric layer is formed on the porous ceramic body for example by oxidation. A conductive medium is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.
摘要翻译: 大容量电容器包括由金属箔形成的第一电极和形成在金属箔上的半导体多孔陶瓷体。 例如通过氧化在多孔陶瓷体上形成电介质层。 导电介质沉积在填充多孔陶瓷体的孔隙并形成第二电极的多孔陶瓷体上。 然后电容器可以用各种层封装,并且可以包括常规的电终端。 制造大容量电容器的方法包括在由金属箔形成的第一电极上形成导电多孔陶瓷体,氧化以形成电介质层,并用导电介质填充多孔体以形成第二电极。 也可以在金属箔和多孔陶瓷体之间设置薄的半导体陶瓷层。
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公开(公告)号:US07426102B2
公开(公告)日:2008-09-16
申请号:US11415039
申请日:2006-05-01
申请人: Haim Goldberger , Reuven Katraro , Doron Gozaly
发明人: Haim Goldberger , Reuven Katraro , Doron Gozaly
IPC分类号: H01G4/228
CPC分类号: H01G4/228 , H01G4/33 , H01L2224/11
摘要: An electronic component such as a capacitor includes a substrate having first and second principal surfaces, a dielectric layer overlaying the first principal surface of the substrate, a first electrode, and a second electrode. There is a passivation layer overlaying the first and second electrodes, a first opening being formed in the passivation layer over the first electrode and a second opening being formed in the passivation layer over the second electrode. A first bottom electrode termination is positioned in the first opening and a second bottom electrode termination is positioned in the second opening. The first bottom electrode termination is electrically connected to the first electrode and the second bottom electrode termination is electrically connected to the second electrode. A standoff is positioned between the first bottom electrode termination and the second bottom electrode termination and attached to the passivation layer to thereby provide support for the electronic component when mounted. The standoff provides resistance to tilting.
摘要翻译: 诸如电容器的电子部件包括具有第一和第二主表面的基板,覆盖基板的第一主表面的电介质层,第一电极和第二电极。 存在覆盖第一和第二电极的钝化层,第一开口形成在第一电极上的钝化层中,第二开口形成在第二电极上的钝化层中。 第一底部电极终端位于第一开口中,而第二底部电极终端位于第二开口中。 第一底部电极端子电连接到第一电极,第二底部电极端子电连接到第二电极。 间隔件位于第一底部电极端子和第二底部电极端子之间并且附接到钝化层,从而在安装时为电子部件提供支撑。 对立提供了对倾斜的抵抗力。
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公开(公告)号:US07642629B2
公开(公告)日:2010-01-05
申请号:US11891867
申请日:2007-08-13
申请人: Gil Zilber , Reuven Katraro , Julia Aksenton , Vage Oganesian
发明人: Gil Zilber , Reuven Katraro , Julia Aksenton , Vage Oganesian
CPC分类号: H01L24/13 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L24/94 , H01L2224/02319 , H01L2224/02321 , H01L2224/02335 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/13099 , H01L2224/274 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
摘要翻译: 一种集成封装的集成电路器件,包括集成电路管芯,该集成电路管芯包括具有第一和第二大致平面的表面和边缘表面的结晶衬底和形成在第一大致平坦表面上的有源表面,形成在有源表面上的至少一个芯片级封装层, 至少一个电触点形成在所述至少一个芯片级封装层上,所述至少一个电触点通过形成在所述第一大致平坦表面上的至少一个焊盘连接到所述有源表面上的电路。
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公开(公告)号:US5039421A
公开(公告)日:1991-08-13
申请号:US415156
申请日:1989-10-02
申请人: Charles Linder , Mordechai Perry , Mara Nemas , Reuven Katraro
发明人: Charles Linder , Mordechai Perry , Mara Nemas , Reuven Katraro
CPC分类号: B01D67/0093 , B01D69/125 , B01D71/42 , B01D71/76 , B01D2323/30
摘要: A composite membrane for separating at least one dissolved or suspended component from a liquid phase, and characterized by solvent stability, comprises:(A) a substrate microfiltration, ultrafiltration or reverse osmosis membrane which has been initially formed from at least one member selected from non-crosslinked acrylonitrile homopolymers and copolymers, and non-crosslinked substituted acrylonitrile homopolymers and copolymers, and which has been subjected to at least one in situ crosslinking reaction; and(B) superimposed upon the substrate membrane, at least one coating including at least one component selected from hydrophilic monomers containing reactive functions, hydrophilic oligomers containing reactive functions and hydrophilic polymers containing reactive functions, such reactive functions having been subjected to a post-coating crosslinking reaction.
摘要翻译: 一种用于从液相中分离至少一种溶解或悬浮组分的复合膜,其特征在于溶剂稳定性,包括:(A)基材微量过滤,超滤或反渗透膜,其最初由至少一种选自非 - 交联的丙烯腈均聚物和共聚物,以及非交联的取代的丙烯腈均聚物和共聚物,并且已经进行了至少一个原位交联反应; 和(B)叠加在基材膜上的至少一种包含至少一种选自包含反应性官能团的亲水性单体的成分,含有反应性官能团的亲水性低聚物和含有反应性官能团的亲水性聚合物的涂层, 交联反应。
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公开(公告)号:US09306056B2
公开(公告)日:2016-04-05
申请号:US12610148
申请日:2009-10-30
申请人: Deva Pattanayak , King Owyang , Mohammed Kasem , Kyle Terrill , Reuven Katraro , Kuo-In Chen , Calvin Choi , Qufei Chen , Ronald Wong , Kam Hong Lui , Robert Xu
发明人: Deva Pattanayak , King Owyang , Mohammed Kasem , Kyle Terrill , Reuven Katraro , Kuo-In Chen , Calvin Choi , Qufei Chen , Ronald Wong , Kam Hong Lui , Robert Xu
CPC分类号: H01L29/7809 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L29/408 , H01L29/41766 , H01L29/45 , H01L29/456 , H01L29/66734 , H01L29/7813 , H01L2224/0401 , H01L2224/05 , H01L2224/05552 , H01L2224/05554 , H01L2224/06051 , H01L2224/13007 , H01L2224/13014 , H01L2224/13023 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/00012 , H01L2924/00
摘要: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.
摘要翻译: 半导体器件(例如,倒装芯片)包括通过中间层与漏极接触分离的衬底层。 通过中间层的沟槽状馈通元件用于在器件工作时电连接漏极接触和衬底层。
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公开(公告)号:US20110101525A1
公开(公告)日:2011-05-05
申请号:US12610148
申请日:2009-10-30
申请人: Deva Pattanayak , King Owyang , Mohammed Kasem , Kyle Terrill , Reuven Katraro , Kuo-In Chen , Calvin Choi , Qufei Chen , Ronald Wong , Kam Hong Lui , Robert Xu
发明人: Deva Pattanayak , King Owyang , Mohammed Kasem , Kyle Terrill , Reuven Katraro , Kuo-In Chen , Calvin Choi , Qufei Chen , Ronald Wong , Kam Hong Lui , Robert Xu
IPC分类号: H01L23/48 , H01L23/488 , H01L21/768
CPC分类号: H01L29/7809 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L29/408 , H01L29/41766 , H01L29/45 , H01L29/456 , H01L29/66734 , H01L29/7813 , H01L2224/0401 , H01L2224/05 , H01L2224/05552 , H01L2224/05554 , H01L2224/06051 , H01L2224/13007 , H01L2224/13014 , H01L2224/13023 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/00012 , H01L2924/00
摘要: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.
摘要翻译: 半导体器件(例如,倒装芯片)包括通过中间层与漏极接触分离的衬底层。 通过中间层的沟槽状馈通元件用于在器件工作时电连接漏极接触和衬底层。
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公开(公告)号:US20070127189A1
公开(公告)日:2007-06-07
申请号:US11293673
申请日:2005-12-02
申请人: Reuven Katraro , Lilia Kushnarev , Nissim Cohen , Haim Goldberger
发明人: Reuven Katraro , Lilia Kushnarev , Nissim Cohen , Haim Goldberger
IPC分类号: H01G4/06
CPC分类号: H01G9/012 , H01G2/065 , H01G9/042 , H01G9/0425 , H01G9/08 , Y10T29/41 , Y10T29/417
摘要: A surface mount chip capacitor includes a metal substrate, a conductive powder element comprising a valve metal and partially surrounding the metal substrate with the metal substrate extending outwardly from the conductive powder towards the anode end of the surface mount chip capacitor, a silver body cathode at least partially surrounding the conductive powder element, a coating formed by vapor-phase deposition surrounding the silver body cathode, an insulative material formed about a portion of the substrate extending outwardly from the conductive powder, a conductive coating formed around the metal substrate at the anode end of the surface mount chip capacitor, an end termination anode electrically connected to the conductive coating at the anode end of the surface mount chip capacitor, and an end termination cathode electrically connected to the silver body cathode at the cathode end of the surface mount chip capacitor.
摘要翻译: 表面安装片式电容器包括金属基板,包括阀金属的导电粉末元件,并且部分地围绕金属基板,金属基板从导电粉末朝向表面安装片式电容器的阳极端向外延伸,银体阴极 至少部分地围绕导电粉末元件,通过围绕银体阴极的气相沉积形成的涂层,围绕从导电粉末向外延伸的部分基板形成的绝缘材料,在阳极处形成在金属基板周围的导电涂层 表面安装片式电容器的端部,与表面贴装电容器的阳极端处的导电涂层电连接的端接端子阳极,以及电连接到表面安装芯片的阴极端处的银体阴极的端部端子阴极 电容器。
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