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公开(公告)号：US20150177820A1
公开(公告)日：2015-06-25
申请号：US14138564
申请日：2013-12-23
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/3275 , G06F1/3287 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a processor includes first logic to determine first power to be provided to a first portion of a computational resource during a time period. The first portion may be reserved for execution by the processor of a first workload to be executed during the time period. The first power may be determined based at least in part on the first workload and independently of a second workload. The processor may include second logic to determine second power to be provided to a second portion of the computational resource during the time period. The second portion may be reserved for execution by the processor of the second workload during the time period. The second power may be determined based at least in part on the second workload and independently of the first workload.
摘要翻译： 在一个实施例中，处理器包括第一逻辑，以在一段时间内确定要提供给计算资源的第一部分的第一功率。 第一部分可以被保留以供处理器执行在该时间段期间执行的第一工作负载。 第一功率可以至少部分地基于第一工作负载并且独立于第二工作负载来确定。 处理器可以包括第二逻辑以确定在该时间周期期间要提供给计算资源的第二部分的第二功率。 在该时间段期间，第二部分可以被保留用于由处理器执行第二工作负载。 可以至少部分地基于第二工作负载并且独立于第一工作负载来确定第二功率。
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公开(公告)号：US20150370564A1
公开(公告)日：2015-12-24
申请号：US14313810
申请日：2014-06-24
CPC分类号： G06F9/30141 , G06F1/3237 , G06F9/30079 , G06F9/3836 , G06F9/3869 , Y02D10/128
摘要： Described is an integrated circuit (IC) comprising: a processor; and a plurality of registers coupled to the processor, wherein the processor to select one of the registers of the plurality to stall execution of an instruction by a predetermined time.
摘要翻译： 描述了一种集成电路（IC），包括：处理器; 以及耦合到所述处理器的多个寄存器，其中所述处理器选择所述多个寄存器中的一个寄存器以将指令的执行停止预定时间。
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公开(公告)号：US20170171645A1
公开(公告)日：2017-06-15
申请号：US14967297
申请日：2015-12-12
申请人： Eli Kupermann , Suryaprasad Kareenahalli , Christian Soby , Amit Kimelman , Rajasekaran Andiappan , Elena Agranovsky
发明人： Eli Kupermann , Suryaprasad Kareenahalli , Christian Soby , Amit Kimelman , Rajasekaran Andiappan , Elena Agranovsky
CPC分类号： H04Q9/00 , G05B15/02 , G06F1/3287 , G06F1/3296 , G06F9/45558 , G06F12/0811 , G06F2009/45575 , G06F2009/45591 , G06F2009/45595 , G06F2212/283
摘要： Described is an apparatus comprising: a processor operable to execute a virtual machine manager (VMM) which is to manage a virtual machine (VM) for a hardware intellectual property (IP) block; a communication fabric; and a hardware IP block coupled to the processor via the communication fabric, wherein the hardware IP block is to be coupled to a first set of one or more sensors, and wherein the VM and the hardware IP block are operable to process data collected from the first set.
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公开(公告)号：US20140019676A1
公开(公告)日：2014-01-16
申请号：US14024724
申请日：2013-09-12
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G11C16/10 , G11C16/32
摘要： A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.
摘要翻译： 控制诸如NAND存储设备的闪存设备的系统和方法可以包括接收执行操作的命令。 响应于确定操作的执行已经完成，存储器件的就绪/忙触点可以被脉冲为低脉冲。
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公开(公告)号：US08521006B2
公开(公告)日：2013-08-27
申请号：US12775003
申请日：2010-05-06
IPC分类号： H04N5/94
CPC分类号： G11B27/3027 , G11B27/28
摘要： Encoded data decoding techniques. A data decoding agent determines a data segment size for a packet that includes a header and a data segment. The data decoding agent determines a segment end location based, at least in part, on the data segment size. The data decoding agent processes subblocks of data from the data segment. The data decoding agent compares a current location to the segment end location to determine if a current subblock of data from the data segments contains the segment end location. The data decoding agent triggers an exception handler if the current subblock contains the segment end location.
摘要翻译： 编码数据解码技术。 数据解码代理确定包括报头和数据段的分组的数据段大小。 数据解码代理至少部分地基于数据段大小来确定段结束位置。 数据解码代理处理来自数据段的数据的子块。 数据解码代理将当前位置与段结束位置进行比较，以确定来自数据段的当前数据子块是否包含段结束位置。 如果当前子块包含段结束位置，则数据解码代理触发异常处理程序。
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公开(公告)号：US20110153914A1
公开(公告)日：2011-06-23
申请号：US12643131
申请日：2009-12-21
CPC分类号： G06F12/0246 , G11C16/10 , G11C16/32
摘要： A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.
摘要翻译： 控制诸如NAND存储设备的闪存设备的系统和方法可以包括接收执行操作的命令。 响应于确定操作的执行已经完成，存储器件的就绪/忙触点可以被脉冲为低脉冲。
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公开(公告)号：US06910114B2
公开(公告)日：2005-06-21
申请号：US10298201
申请日：2002-11-15
CPC分类号： G06F13/1689 , G06F12/0215
摘要： Embodiments of the present invention provide for adaptively tuning the memory idle timer value in real time. Selected memory idle clock cycles are sampled to dynamically determine an optimized memory idle timer value. To optimize latency during sampling, the number of page hits (NPH) and number of page misses (NPM) are multiplied by weighted values WPH and WPM, respectively, such that the weighted function (WPH*NPH)−(WPM*NPM) is maximized. The weight associated with a page miss (WPM) is greater than the weight associated with a page hit (WPH), resulting in a bigger penalty for a page miss than a page hit. The selected setting is continuously optimized.
摘要翻译： 本发明的实施例提供了实时自适应地调整存储器空闲定时器值。 选择的存储器空闲时钟周期被采样以动态地确定优化的存储器空闲定时器值。 为了优化采样期间的等待时间，页面命中次数（N＆lt; PH＆lt; / SUB）和页错失次数（N＆lt; PM＆lt;＆lt;＆gt;）与加权值W < SUB＆gt;和W＆gt; PM＆lt;＆lt;＆lt;＆lt;＆lt;＆lt;＆lt;＆lt;＆lt; SUB> * N ）最大化。 与页面未命中相关联的权重（W SUB PM）大于与页面命中相关联的权重（W＆lt; PH＆lt;＆lt;＆lt;＆lt;＆lt;＆lt;＆gt;），导致页错误的惩罚更大 一个页面命中。 所选设置不断优化。
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公开(公告)号：US09100693B2
公开(公告)日：2015-08-04
申请号：US12796502
申请日：2010-06-08
IPC分类号： H04L29/06 , H04N21/4405 , H04N21/426 , H04N21/4408 , G06F21/10
CPC分类号： H04N21/4405 , G06F21/10 , H04N21/4181 , H04N21/42623 , H04N21/4408
摘要： An apparatus for secured playback is presented. In one embodiment, the apparatus includes a controller that includes a key derivation module to manage authentication and key derivation. In one embodiment, the apparatus provides a video decryption key to a graphics engine if video data portions in a data stream are retrievable without having to decrypt the data stream. In one embodiment, the apparatus also includes a decryption module to decrypt a part of data in conjunction with an encryption key to generate video information and video data. The controller then writes an encrypted version of the video data to a video buffer of a graphics engine.
摘要翻译： 提出了一种用于安全播放的设备。 在一个实施例中，该装置包括控制器，其包括用于管理认证和密钥推导的密钥导出模块。 在一个实施例中，如果可以检索数据流中的视频数据部分而不必对数据流进行解密，则该装置向图形引擎提供视频解密密钥。 在一个实施例中，该装置还包括解密模块，用于结合加密密钥对一部分数据进行解密以产生视频信息和视频数据。 然后，控制器将视频数据的加密版本写入图形引擎的视频缓冲器。
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9.发明授权Method, apparatus and system for reduced channel starvation in a DMA engine 有权用于减少DMA引擎中信道不足的方法，装置和系统公开(公告)号：US08250253B2
公开(公告)日：2012-08-21
申请号：US12822046
申请日：2010-06-23
IPC分类号： G06F13/28
CPC分类号： G06F13/30
摘要： Techniques for generating information identifying a next direct memory access (DMA) task to be serviced. In an embodiment, arbitration logic provides a sequence of masking logic to determine, according to a hierarchy of rules, a next task to be serviced by a DMA engine. In certain embodiments, masking logic includes logic to mask information representing pending tasks to be serviced, the masking based on identification of a channel as being a suspended channel and/or a victim channel.
摘要翻译： 用于产生识别要维修的下一个直接存储器访问（DMA）任务的信息的技术。 在一个实施例中，仲裁逻辑提供了一系列屏蔽逻辑，以根据规则层级确定要由DMA引擎服务的下一个任务。 在某些实施例中，掩蔽逻辑包括屏蔽用于表示待服务的待处理任务的信息的逻辑，基于信道识别为暂停信道和/或受害信道的掩蔽。
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公开(公告)号：US20120155633A1
公开(公告)日：2012-06-21
申请号：US12971210
申请日：2010-12-17
IPC分类号： H04L9/28
CPC分类号： H04L9/0822 , H04L9/3263 , H04L2209/60
摘要： In some embodiments an embedded processor is to participate in cryptographic key exchange with an audio software application, and a key exchange communication path is coupled between the audio software application and the embedded processor. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，嵌入式处理器将参与与音频软件应用的加密密钥交换，并且密钥交换通信路径耦合在音频软件应用和嵌入式处理器之间。 描述和要求保护其他实施例。
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