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公开(公告)号：US06480436B2
公开(公告)日：2002-11-12
申请号：US09909467
申请日：2001-07-19
IPC分类号： G11C700
CPC分类号： G11C16/30
摘要： A semiconductor memory includes a plurality of memory cells connected to one another to form a matrix of memory cells. A charge pump is connected to the matrix of memory cells. A plurality of controllable connection elements are provided, with each controllable connection element connected between an output terminal of the charge pump and a respective column line. Connected to the output of the charge pump is the series connection of a first element equivalent to a controllable connection element, and a second element equivalent to a memory cell in a predetermined biasing condition. A voltage regulator is connected between the second equivalent element and the input terminal of the charge pump for regulating the output voltage therefrom based upon a voltage present between terminals of the second equivalent element.
摘要翻译： 半导体存储器包括彼此连接以形成存储器单元矩阵的多个存储单元。 电荷泵连接到存储器单元的矩阵。 提供多个可控制的连接元件，每个可控制的连接元件连接在电荷泵的输出端和相应的列线之间。 连接到电荷泵的输出端是等效于可控制连接元件的第一元件和等同于预定偏压状态下的存储器单元的第二元件的串联连接。 电压调节器连接在第二等效元件和电荷泵的输入端之间，用于基于第二等效元件的端子之间存在的电压来调节其输出电压。
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2.发明授权Non-volatile memory device with burst mode reading and corresponding reading method 有权具有突发模式读取的非易失性存储器件和相应的读取方法公开(公告)号：US06854040B1
公开(公告)日：2005-02-08
申请号：US09717938
申请日：2000-11-21
申请人： Simone Bartoli , Antonino Geraci , Mauro Sali , Lorenzo Bedarida
发明人： Simone Bartoli , Antonino Geraci , Mauro Sali , Lorenzo Bedarida
CPC分类号： G11C7/1072 , G11C7/1033 , G11C7/1045
摘要： A read control circuit and a reading method for an electronic memory device integrated on a semiconductor includes a non-volatile memory matrix with associated row and column decoders connected to respective outputs of an address counter. An address transition detect (ATD) circuit detects an input transition as the memory device is being accessed, and read amplifiers and attendant registers transfer the data read from the memory matrix to the output. The read control circuit includes a detection circuit to which is input a clock signal and a logic signal to enable reading in the burst mode. A burst read mode control logic circuit is connected downstream of the detection circuit. The method includes accessing the memory matrix in a random read mode, detecting a request for access in the burst read mode, and executing the parallel reading of a plurality of memory words during a single period of time clocked by the clock signal.
摘要翻译： 集成在半导体上的电子存储装置的读取控制电路和读取方法包括具有连接到地址计数器的相应输出的相关联的行和列解码器的非易失性存储器矩阵。 地址转换检测（ATD）电路在正在访问存储器件时检测输入转换，并且读取放大器和伴随寄存器将从存储器矩阵读取的数据传送到输出。 读取控制电路包括检测电路，在该检测电路中输入时钟信号和逻辑信号，使得能够以突发模式进行读取。 突发读模式控制逻辑电路连接在检测电路的下游。 该方法包括以随机读取模式访问存储器矩阵，以突发读取模式检测访问请求，以及在由时钟信号计时的单个时间段内执行多个存储器字的并行读取。
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3.发明授权Architecture for handling internal voltages in a non-volatile memory, particularly in a single-voltage supply type of dual-work flash memory 有权用于处理非易失性存储器内部电压的架构，特别是在单电源类型的双工作闪存中公开(公告)号：US06385107B1
公开(公告)日：2002-05-07
申请号：US09710067
申请日：2000-11-09
申请人： Lorenzo Bedarida , Simone Bartoli , Mauro Sali , Antonio Russo
发明人： Lorenzo Bedarida , Simone Bartoli , Mauro Sali , Antonio Russo
IPC分类号： G11C702
摘要： An architecture handles internal voltages in a non-volatile memory array which is split into at least first and second mutually independent banks. The architecture includes first and second pluralities of generators for generating at least one of the internal voltages, which are separate from each other and connected to the first and second banks, respectively, of the nonvolatile memory array; and a control system connected to the pluralities of generators to handle the correct activation of the different generators in the different conditions of the memory array operation.
摘要翻译： 架构处理非易失性存储器阵列中的内部电压，其被分成至少第一和第二相互独立的存储体。 该结构包括用于产生彼此分离并分别连接到非易失性存储器阵列的第一和第二组的内部电压中的至少一个的第一和第二多个发生器; 以及连接到多个发电机的控制系统，以在存储器阵列操作的不同条件下处理不同发电机的正确激活。
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4.发明授权Non-volatile memory with functional capability of simultaneous modification of the content and burst mode read or page mode read 有权具有同时修改内容和突发模式读取或页面模式读取功能的非易失性存储器公开(公告)号：US06912598B1
公开(公告)日：2005-06-28
申请号：US09627703
申请日：2000-07-28
申请人： Lorenzo Bedarida , Antonino Geraci , Mauro Sali , Simone Bartoli
发明人： Lorenzo Bedarida , Antonino Geraci , Mauro Sali , Simone Bartoli
摘要： An electrically alterable semiconductor memory comprises at least two substantially independent memory banks, and a first control circuit for controlling operations of electrical alteration of the content of the memory. The first control circuit permits the selective execution of an operation of electrical alteration of the content of one of the at least two memory banks. The memory also comprises second control circuit that permits, simultaneously with said operation of electrical alteration of the content of one of the at least two memory banks, a burst mode, page mode, or standard read operation for reading the content of the other memory bank.
摘要翻译： 一种电可更改的半导体存储器包括至少两个基本上独立的存储体，以及第一控制电路，用于控制存储器内容的电气改变的操作。 第一控制电路允许选择性地执行对至少两个存储体之一的内容的电气改变的操作。 存储器还包括第二控制电路，其允许同时对所述至少两个存储器组之一的内容进行电气改变的所述操作，用于读取另一个存储体的内容的突发模式，寻呼模式或标准读取操作 。
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5.发明授权Non-volatile memory with functional capability of burst mode read and page mode read during suspension of an operation of electrical alteration 有权在电气变更操作暂停期间读取突发模式读取和页面模式的功能性能的非易失性存储器公开(公告)号：US06442068B1
公开(公告)日：2002-08-27
申请号：US09619589
申请日：2000-07-19
申请人： Simone Bartoli , Lorenzo Bedarida , Mauro Sali , Antonio Russo
发明人： Simone Bartoli , Lorenzo Bedarida , Mauro Sali , Antonio Russo
IPC分类号： G11C1134
CPC分类号： G11C16/26 , G11C16/10 , G11C2216/20
摘要： An electrically alterable semiconductor memory includes at least two memory sectors the content of which is individually alterable, and a control circuit for controlling operations of electrical alteration of the content of the memory, permitting the selective execution of an operation of electrical alteration of the content of one of the memory sectors with the possibility of suspending the execution to permit read access to the other of the memory sectors. The control circuit is also capable of permitting, during the suspension, an operation of burst mode or page mode reading of the content of the other memory sector.
摘要翻译： 电可改变的半导体存储器包括至少两个存储器扇区，其内容是可单独改变的;以及控制电路，用于控制存储器内容的电气改变的操作，允许选择性地执行对内容的电气改变的操作 其中一个存储器扇区具有暂停执行以允许对另一个存储器扇区的读取访问的可能性。 控制电路还能够在暂停期间允许对其他存储器扇区的内容的突发模式或页面模式读取的操作。
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6.发明授权Method for reading data from a non-volatile memory device with autodetect burst mode reading and corresponding reading circuit 失效从具有自动检测突发模式读取的非易失性存储器件读取数据的方法和相应的读取电路公开(公告)号：US06349059B1
公开(公告)日：2002-02-19
申请号：US09716746
申请日：2000-11-20
申请人： Simone Bartoli , Antonio Geraci , Mauro Sali , Lorenzo Bedarida
发明人： Simone Bartoli , Antonio Geraci , Mauro Sali , Lorenzo Bedarida
IPC分类号： G11C1604
CPC分类号： G11C7/1033 , G11C7/1045 , G11C7/1072
摘要： A method for reading data from an integrated electronic memory device including a non-volatile memory matrix includes supplying the memory with an address of a memory location where a reading is to be effected, accessing the memory matrix in a random read mode, supplying the memory with a clock signal and an address acknowledge signal (LAN), detecting a request for burst read mode access, and starting the burst reading as the clock signal shows a rising edge. A related circuit is also provided.
摘要翻译： 一种用于从包括非易失性存储器矩阵的集成电子存储器件读取数据的方法包括向存储器提供要进行读取的存储器位置的地址，以随机读取模式访问存储器矩阵，提供存储器 具有时钟信号和地址确认信号（LAN），检测对突发读取模式存取的请求，以及当时钟信号显示上升沿时启动突发读取。 还提供了相关的电路。
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公开(公告)号：US07782695B2
公开(公告)日：2010-08-24
申请号：US11652742
申请日：2007-01-12
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C7/02 , G11C7/067 , G11C16/26 , G11C2207/063
摘要： A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.
摘要翻译： 具有电流偏移功能的感测电路。 在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。 感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。 感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。 根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。
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公开(公告)号：US07561485B2
公开(公告)日：2009-07-14
申请号：US11652771
申请日：2007-01-12
IPC分类号： G11C7/02
CPC分类号： G11C16/28
摘要： A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier, where the second bitline produces a second transient current that is equal to the first transient current. The sense amplifier enables the first and second transient currents to be canceled. According to the system disclosed herein, the state of a memory cell may be determined without being adversely affected by transient currents.
摘要翻译： 公开了一种存储系统。 在一个实施例中，存储器系统包括第一位线，其中第一位线产生第一瞬态电流。 存储器系统还包括耦合到第一位线的读出放大器。 存储器系统还包括耦合到读出放大器的第二位线，其中第二位线产生等于第一瞬态电流的第二瞬态电流。 读出放大器能够消除第一和第二瞬态电流。 根据本文公开的系统，可以确定存储器单元的状态而不受瞬态电流的不利影响。
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9.发明授权公开(公告)号：US07158415B2
公开(公告)日：2007-01-02
申请号：US11089268
申请日：2005-03-24
IPC分类号： G11C16/10
CPC分类号： G11C29/028 , G11C16/04 , G11C29/24 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： An embedded circuit in a memory device is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells. An external test device programs at least one reference cell to a predetermined value. The embedded circuit uses the cell programmed by the external device as a comparative reference to program additional reference cells.
摘要翻译： 使用存储器件中的嵌入式电路来代替外部测试装置来执行耗费时间的任务，例如参考单元设置期间的电压验证。 外部测试装置将至少一个参考单元编程为预定值。 嵌入式电路使用由外部设备编程的单元作为比较参考来编程附加参考单元。
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10.发明申请公开(公告)号：US20060279988A1
公开(公告)日：2006-12-14
申请号：US11193924
申请日：2005-07-28
申请人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
发明人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译： 用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。 存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。 参考矩阵耦合到存储器矩阵并具有参考单元。 逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。
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