摘要:
A method for producing a bipolar transistor completely surrounded by an insulating trench in a substrate. Insulating regions at the surface of the substrate can be produced by depositing an SiO.sub.2 layer on the basis of thermal decomposition of TEOS and subsequent structuring of the SiO.sub.2 layer. The insulating regions can be employed as a self-aligning mask for the production of a collector terminal and of a substrate terminal.
摘要:
A process for producing components having a contact structure provides for vertical contact-making, in which, for the connection of a metal contact of a first component to a metal contact of a second component, the substrate is etched out, starting from the top, in a region provided for a vertical, conductive connection, this recess is filled with a metal so that said metal is connected to the surface of the metal contact, the rear side of the substrate is removed until the metal projects beyond the rear side, a metallization layer made of a metal having a low melting point, for example AuIn, is applied to the metal contact of the second component, the surface of the second component is provided with a planar layer, the two components are arranged vertically with respect to one another and a permanent contact is produced between the metal of the first component and the metallization layer of the second component by pressing one onto the other and heating.
摘要:
An element that prevents the formation of a channel is arranged in a level of the channel region (Kaa) at one of two opposite sidewalls of a semiconductor structure that has a source/drain region (S/D1a) and a channel region (Kaa) of a vertical selection transistor arranged therebelow. The source/drain region as well as a respective word line (W1a) adjoin at both sidewalls. For folded bit lines (B1a), respectively two word lines (W1a) can be formed in the trenches (G2a). The elements of semiconductor structures neighboring along one of the trenches (G2a) are then arranged in alternation at a sidewall of the trench (G2a) and at a sidewall of a neighboring trench (D2a). A storage capacitor can be arranged over a substrate (1a) or can be buried in the substrate (1a). The connection of the selection transistor to a bit line (B1a) can ensue in many ways.
摘要:
A terminal metallization (8) is applied onto and structured on a layer structure on the upper side of the component, the terminal metallization is applied on the upper side of an insulating layer (7) with an opening on a metallization (6) provided for electrical connection. By filling a hole produced in a covering dielectric with metal, a contact rod (12) seated on this terminal metallization (8) is formed. This contact rod is resiliently movable in a surrounding opening (14) of the component on the free part of the terminal metallization (8) anchored in the layer structure. This enables the reversible contacting of the component to a further component arranged vertically thereto, whereby the planar upper sides lying opposite one another can be brought into intimate contact because the contact rod (12) pressed against a contact (15) of the other component is pressed back into the opening (14) and an adequately firm connection of the contacts is achieved by the spring power of the terminal metallization (8).
摘要:
A memory cell array has memory cells in which there is an electrical connection between a polycrystalline semiconductor material of a capacitor electrode and a monocrystalline semiconductor region. Islands made of an amorphous material are disposed in a vicinity of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands are produced in particular by thermally breaking up an amorphous layer which has been formed by thermal oxidation. The memory cell array is in particular a DRAM array with a trench capacitor.
摘要:
A read-only memory cell device includes a substrate formed of semiconductor material and having a main area. Memory cells in the vicinity of the main area are disposed in matrix form in columns and rows in a cell field. Each memory cell has in each case at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode. The MOS transistors of a column are connected in series one after the other. Each column is connected to a bit line and the gate electrodes of the MOS transistors of a row are connected to a word line. The source and drain regions of the MOS transistors of a column are formed in source/drain webs running substantially parallel to one another at a predetermined spacing, are electrically insulated from one another, are produced from the semiconductor material of the substrate and have a predetermined web depth, starting from the main area of the substrate. The word lines for connection of the gate electrodes of the MOS transistors run transversely with respect to the longitudinal direction of the source/drain webs.
摘要:
To produce a three-dimensional circuit arrangement, a first substrate (1) is thinned, stacked onto a second substrate (2) and fixedly connected to the latter. The first substrate (1) and the second substrate (2) in this case each comprise circuit structures (12, 22) and metallization planes (13, 23). At least one first contact hole (16) and one second contact hole (4) are opened, which reach the metallization plane (13, 23) in the first substrate (1) and second substrate (2), respectively, the second contact hole (4) passing through the first substrate (1). The metallization planes (13, 23) of the two substrates (1, 2) are electrically connected to one another via a conductive layer (7).
摘要:
Manufacturing method for lateral bipolar transistors, wherein a highly doped emitter zone and collector zone as well as a base terminal zone are manufactured in a region in the silicon layer of a SOI substrate having a basic doping. The zones are manufactured by implantation using a mask. A base zone is then produced by implantation of dopant using the mask. The base zone is produced between the emitter zone and the collector zone.
摘要:
Method for manufacturing lateral bipolar transistors on a SOI substrate, whereby a basic doping for the conductivity type of emitter and collector is produced in the silicon layer of this SOI substrate, insulation regions are produced outside the region provided for the transistor, contact layers and dielectric layers are applied over a highly doped emitter zone and over a highly doped collector zone produced by a mask technique and are structured, so that a trench is located over a base zone to be produced and in the middle between emitter zone and collector zone, an auxiliary layer is then conformally deposited surface-wide with constant thickness, as a result whereof the trench having the width is reduced to a gap having the width of the base zone to be produced, an implantation of dopant for the operational sign of the conductivity of the base is undertaken through this gap, the regions situated laterally relative to this base zone are shielded by the vertical portions of the auxiliary layer that cover the sidewalls of the trench, via holes are then etched into the auxiliary layer and into the dielectric layer and metal contacts are produced for the electrical connection of emitter, collector and base.
摘要:
A method and apparatus for the reversible contacting of a semiconductor circuit level to assist in performing a function test. The apparatus includes a testing head having test points arranged at a test side lying opposite the contact surfaces of a semiconductor circuit level. The test points are formed of liquid contacts in recesses in the test side of the testing head wherein the liquid contacts form menisci that project beyond the surface of the testing head. The recesses, in turn, are provided for metallizations which are connected to electrically-conductive leads. In addition, the surface may be provided with a roughening or with etched trenches.