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    Low power display mode
    1.
    发明授权
    Low power display mode 有权
    低功耗显示模式

    公开(公告)号：US08314806B2

    公开(公告)日：2012-11-20

    申请号：US11322880

    申请日：2006-04-13

    Applicant: Eric Samson ,  Aditya Navale ,  Todd Witter

    Inventor： Eric Samson ,  Aditya Navale ,  Todd Witter

    IPC: G09G5/39

    CPC classification number: G06F3/14 ,  G09G5/006 ,  G09G5/008 ,  G09G5/363 ,  G09G5/39 ,  G09G2330/021

    Abstract: A controller is described that includes wiring to transport notification that a FIFO that holds data to be used to display content on a display has reached a threshold. The controller also includes first control circuitry to turn on a phase locked loop (PLL) circuit to cause logic circuitry within the controller downstream from the PLL to begin to receive a first clock in response to the notification. The logic circuitry is to transport data read from a memory toward the FIFO. The controller also includes second control circuitry to cause the memory to use a second clock provided by the controller in response to the notification.

    Abstract translation: 描述了一种控制器，其包括用于传送通知的连接，即在显示器上保存用于显示内容的数据的FIFO已经达到阈值。 该控制器还包括第一控制电路，用于接通锁相环（PLL）电路，以使PLL内的控制器内的逻辑电路响应该通知开始接收第一时钟。 逻辑电路是将从存储器读取的数据传输到FIFO。 控制器还包括第二控制电路，以使存储器响应于该通知使用由控制器提供的第二时钟。

    Method and apparatus for dynamic DLL powerdown and memory self-refresh
    3.
    发明申请
    Method and apparatus for dynamic DLL powerdown and memory self-refresh 有权
    用于动态DLL掉电和内存自刷新的方法和装置

    公开(公告)号：US20060020835A1

    公开(公告)日：2006-01-26

    申请号：US10899530

    申请日：2004-07-26

    Applicant: Eric Samson ,  Aditya Navale ,  Leslie Cline

    Inventor： Eric Samson ,  Aditya Navale ,  Leslie Cline

    IPC: G06F1/26

    CPC classification number: G06F1/3225

    Abstract: Embodiments of the present invention provide a method and apparatus for conserving power in an electronic device. In particular, embodiments of the present invention dynamically place the memory in self-refresh and chipset clock circuits in power down mode while keeping the isochronous streams (such as display) updated and servicing bus master cycles in a power savings mode.

    Abstract translation: 本发明的实施例提供了一种用于在电子设备中节省功率的方法和装置。 特别地，本发明的实施例将存储器动态地将自刷新和芯片组时钟电路放置在断电模式中，同时保持同步流（例如显示）被更新并且在节电模式下维持总线主控周期。

    Low power display mode
    4.
    发明申请
    Low power display mode 有权
    低功耗显示模式

    公开(公告)号：US20070242076A1

    公开(公告)日：2007-10-18

    申请号：US11322880

    申请日：2006-04-13

    Applicant: Eric Samson ,  Aditya Navale ,  Todd Witter

    Inventor： Eric Samson ,  Aditya Navale ,  Todd Witter

    IPC: G06F13/372

    CPC classification number: G06F3/14 ,  G09G5/006 ,  G09G5/008 ,  G09G5/363 ,  G09G5/39 ,  G09G2330/021

    Abstract: A controller is described that includes wiring to transport notification that a FIFO that holds data to be used to display content on a display has reached a threshold. The controller also includes first control circuitry to turn on a phase locked loop (PLL) circuit to cause logic circuitry within the controller downstream from the PLL to begin to receive a first clock in response to the notification. The logic circuitry is to transport data read from a memory toward the FIFO. The controller also includes second control circuitry to cause the memory to use a second clock provided by the controller in response to the notification.

    Abstract translation: 描述了一种控制器，其包括用于传送通知的连接，即在显示器上保存用于显示内容的数据的FIFO已经达到阈值。 该控制器还包括第一控制电路，用于接通锁相环（PLL）电路，以使PLL内的控制器内的逻辑电路响应该通知开始接收第一时钟。 逻辑电路是将从存储器读取的数据传输到FIFO。 控制器还包括第二控制电路，以使存储器响应于该通知使用由控制器提供的第二时钟。

    Dynamic error handling using parity and redundant rows
    6.
    发明授权
    Dynamic error handling using parity and redundant rows 有权
    使用奇偶校验和冗余行的动态错误处理

    公开(公告)号：US09075741B2

    公开(公告)日：2015-07-07

    申请号：US13327845

    申请日：2011-12-16

    Applicant: Altug Koker ,  Shailesh Shah ,  Aditya Navale ,  Murali Ramadoss ,  Satish K. Damaraju

    Inventor： Altug Koker ,  Shailesh Shah ,  Aditya Navale ,  Murali Ramadoss ,  Satish K. Damaraju

    IPC: G06F11/00 ,  G06F11/10 ,  H03M13/09 ,  H04L1/00 ,  H03M13/11

    CPC classification number: G06F11/1048 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1076 ,  H03M13/09 ,  H03M13/11 ,  H04L1/0057

    Abstract: Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.

    Abstract translation: 公开了使用奇偶校验和冗余行的动态纠错的发明的实施例。 在一个实施例中，装置包括存储结构，奇偶校验逻辑，错误存储空间和错误事件发生器。 存储结构是存储多个数据值。 奇偶校验逻辑是检测存储在存储结构中的数据值中的奇偶校验错误。 错误存储空间是存储奇偶校验错误检测的指示。 错误事件发生器响应于存储在错误存储空间中的奇偶校验错误的指示而生成事件。

    METHOD AND APPARATUS FOR SUPPORTING PROGRAMMABLE SOFTWARE CONTEXT STATE EXECUTION DURING HARDWARE CONTEXT RESTORE FLOW
    7.
    发明申请
    METHOD AND APPARATUS FOR SUPPORTING PROGRAMMABLE SOFTWARE CONTEXT STATE EXECUTION DURING HARDWARE CONTEXT RESTORE FLOW 有权
    在硬件上下文恢复流程期间支持可编程软件上下文执行的方法和装置

    公开(公告)号：US20150123980A1

    公开(公告)日：2015-05-07

    申请号：US14072622

    申请日：2013-11-05

    Applicant: Hema Chand Nalluri ,  Jeffery S. Boles ,  Murali Ramadoss ,  Aditya Navale ,  Lalit K. Saptarshi

    Inventor： Hema Chand Nalluri ,  Jeffery S. Boles ,  Murali Ramadoss ,  Aditya Navale ,  Lalit K. Saptarshi

    IPC: G06T15/00 ,  G06F9/46 ,  G06T1/20

    CPC classification number: G06F9/461 ,  G06T1/20

    Abstract: A method and apparatus for supporting programmable software context state execution during hardware context restore flow is described. In one example, a context ID is assigned to graphics applications including a unique context memory buffer, a unique indirect context pointer and a corresponding size to each context ID, an indirect context offset, and an indirect context buffer address range. When execution of the first context workload is indirected, the state of the first context workload is saved to the assigned context memory buffer. The indirect context pointer, the indirect context offset and a size of the indirect context buffer address range are saved to registers that are independent of the saved context state. The context is restored by accessing the saved indirect context pointer, the indirect context offset and the buffer size.

    Abstract translation: 描述了用于在硬件上下文恢复流程期间支持可编程软件上下文状态执行的方法和装置。 在一个示例中，上下文ID被分配给包括唯一上下文存储器缓冲器，唯一间接上下文指针和对每个上下文ID，间接上下文偏移以及间接上下文缓冲器地址范围的对应大小的图形应用。 当第一上下文工作负载的执行被间接时，第一上下文工作负载的状态被保存到所分配的上下文存储器缓冲器中。 间接上下文指针，间接上下文偏移量和间接上下文缓冲区地址范围的大小保存到独立于保存的上下文状态的寄存器中。 通过访问保存的间接上下文指针，间接上下文偏移量和缓冲区大小来恢复上下文。

    MEMORY MAPPING FOR A GRAPHICS PROCESSING UNIT
    8.
    发明申请
    MEMORY MAPPING FOR A GRAPHICS PROCESSING UNIT 有权
    图形处理单元的存储映射

    公开(公告)号：US20140267323A1

    公开(公告)日：2014-09-18

    申请号：US13851400

    申请日：2013-03-27

    Applicant: Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Aditya Navale

    Inventor： Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Aditya Navale

    IPC: G06T1/60

    CPC classification number: G06T1/60 ,  G06F9/485 ,  G06F12/1009 ,  G06F12/128 ,  G06T1/20

    Abstract: An electronic device is described herein. The electronic device may include a page walker module to receive a page request of a graphics processing unit (GPU). The page walker module may detect a page fault associated with the page request. The electronic device may include a controller, at least partially comprising hardware logic. The controller is to monitor execution of the page request having the page fault. The controller determines whether to suspend execution of a work item at the GPU associated with the page request having the page fault, or to continue execution of the work item based on factors associated with the page request.

    Abstract translation: 本文描述了一种电子设备。 电子设备可以包括页面助行器模块，用于接收图形处理单元（GPU）的页面请求。 页面助行器模块可以检测与页面请求相关联的页面错误。 电子设备可以包括至少部分地包括硬件逻辑的控制器。 控制器将监视具有页面错误的页面请求的执行。 控制器确定是否在与具有页面错误的页面请求相关联的GPU处挂起工作项的执行，或者基于与页面请求相关联的因素来继续执行工作项。

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