公开(公告)号：US07115426B2

公开(公告)日：2006-10-03

申请号：US11031423

申请日：2005-01-07

申请人： Erwan Le Roy ,  Patricia Le Coupanec ,  Theodore R. Lundquist ,  William B. Thompson ,  Mark A. Thompson ,  Lokesh Johri

发明人： Erwan Le Roy ,  Patricia Le Coupanec ,  Theodore R. Lundquist ,  William B. Thompson ,  Mark A. Thompson ,  Lokesh Johri

IPC分类号： H01L21/66

CPC分类号： H01L22/12

摘要： A method for utilizing interference fringe patterns generated when milling a trench through a semiconductor substrate by a method such as FIB milling, to determine and optimize the thickness uniformity of the trench bottom. The interference fringes may be mapped and the mapping used to direct the FIB milling to those regions which are thicker to correct observed non-uniformities in the trench floor thickness by varying the pixel dwell time across the milled area. The interference fringe mapping may be used to develop computerized contour lines to automate the pixel dwell time variations as described above, for correcting non-uniformities in the trench floor thickness. The method may be applied to applications other than trench formation for backside editing, such as monitoring progress in forming a milled object.

公开(公告)号：US06855622B2

公开(公告)日：2005-02-15

申请号：US10160606

申请日：2002-05-30

申请人： Erwan Le Roy ,  Mark A. Thompson

发明人： Erwan Le Roy ,  Mark A. Thompson

IPC分类号： H01J37/30 ,  H01J37/305 ,  H01L21/263 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/425

CPC分类号： H01J37/3005 ,  H01J37/228 ,  H01J37/3056 ,  H01J2237/2482 ,  H01J2237/30455 ,  H01J2237/31737 ,  H01J2237/3174 ,  H01J2237/31744 ,  H01L21/2633 ,  H01L21/26506 ,  H01L21/3065 ,  H01L21/31105

摘要： Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The floor of the trench is formed so as to be as smooth and planar as possible, thereby preventing undesirable exposure of the underlying active regions through any unknown or undesired cavity caused by scratches or pits or a deeper than desired sidewall. The smoothness and planarity of the floor of the trench is established by, prior to forming the trench, removing any surface defect initially present by using an FIB etching without use of assist gas to eliminate most scratches or impurities on the surface of the silicon, followed by removal of implanted ions using a gas-injected assisted FIB etch. Then the actual trench is formed using an assisted etch using a more aggressive injected gas.

摘要翻译： 用于从集成电路衬底的背面暴露诸如金属化层的选定部分的集成电路器件的选定特征的装置和方法，而不干扰诸如有源半导体区域的器件的相邻特征。 这是通过FIB（聚焦离子束）蚀刻工艺结合光学显微镜的观察来进行的，以通过衬底形成沟槽。 沟槽的底部形成为尽可能平坦和平坦，从而防止潜在的有源区域通过由划痕或凹坑或更深于期望的侧壁引起的任何未知或不期望的空腔的不希望的暴露。 通过在形成沟槽之前，通过使用FIB蚀刻而不使用辅助气体来除去最初存在的任何表面缺陷，以消除硅表面上的大多数划痕或杂质，建立沟槽底板的平滑度和平坦度，随后 通过使用气体注入的辅助FIB蚀刻去除注入的离子。 然后使用更积极的注入气体的辅助蚀刻形成实际沟槽。

公开(公告)号：US20070293052A1

公开(公告)日：2007-12-20

申请号：US11754466

申请日：2007-05-29

申请人： Erwan Le Roy ,  Chun-Cheng Tsao ,  Theodore Lundquist ,  Rajesh Jain

发明人： Erwan Le Roy ,  Chun-Cheng Tsao ,  Theodore Lundquist ,  Rajesh Jain

IPC分类号： H01L21/302

CPC分类号： H01L21/3065 ,  H01J37/228 ,  H01J37/3056 ,  H01J2237/2482 ,  H01J2237/30466 ,  H01J2237/31749 ,  H01L22/12 ,  H01L22/26

摘要： An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection and/or characteristics of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Resulting fringes will be a function, in part, of the thickness and/or profile of the trench floor. Milling may be controlled as a function of the detected fringe patterns.

摘要翻译： 一种使用光学干涉条纹处理集成电路的装置和方法。 在处理期间，一个或多个波长的光被引导到集成电路上，并且基于干涉条纹和其特性的检测，可以控制进一步的处理。 一种实施方案涉及集成电路的带电粒子束处理，作为干涉条纹的检测和/或特征的函数。 在集成电路的衬底中或其上执行带电粒子束沟槽铣削操作。 光线指向沟槽的地板。 干涉条纹可以由从地板反射的光与来自电路结构的光之间的建构性或破坏性干扰形成。 所产生的条纹将部分地是沟槽地板的厚度和/或轮廓的函数。 作为检测到的条纹图案的函数可以控制铣削。

公开(公告)号：US07135123B1

公开(公告)日：2006-11-14

申请号：US10758146

申请日：2004-01-14

申请人： Mark Alan Thompson ,  Erwan Le Roy ,  Theodore Lundquist ,  William B. Thompson ,  Catherine Kardach

发明人： Mark Alan Thompson ,  Erwan Le Roy ,  Theodore Lundquist ,  William B. Thompson ,  Catherine Kardach

IPC分类号： G01L21/30 ,  H01L21/00

CPC分类号： G01R31/2898 ,  G01R31/307 ,  H01L21/3043 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

摘要： The backside navigation method of the present invention includes milling a fiducial opening through the substrate of an integrated circuit. The milling process is stopped when the fiducial opening reaches the bottom of a trench isolation structure. The trench isolation structure delineated by the fiducial opening may be imaged and registered to a computer aided design layout image to achieve sub-micron navigation resolution.

摘要翻译： 本发明的背面导航方法包括通过集成电路的基板铣削基准开口。 当基准开口到达沟槽隔离结构的底部时，铣削过程停止。 由基准开口划定的沟槽隔离结构可以被成像并记录到计算机辅助设计布局图像中以实现亚微米导航分辨率。

公开(公告)号：US07036109B1

公开(公告)日：2006-04-25

申请号：US10274431

申请日：2002-10-17

申请人： Chun-Cheng Tsao ,  Theodore R. Lundquist ,  William Thompson ,  Erwan Le Roy ,  Eugene A. Delenia

发明人： Chun-Cheng Tsao ,  Theodore R. Lundquist ,  William Thompson ,  Erwan Le Roy ,  Eugene A. Delenia

IPC分类号： G06F17/50

CPC分类号： H01J37/3056 ,  H01J2237/3174

摘要： Methods and apparatus for integrated circuit diagnosis, characterization or modification using a focused ion beam. A method for editing an integrated circuit includes acquiring an image of structures of an integrated circuit by applying a focused ion beam to an outer surface of the integrated circuit to visualize structures beneath the outer surface of the integrated circuit. The method includes using the image to find a location of a circuit element in the integrated circuit and then performing one or more editing operations on the circuit element by applying a focused ion beam to the location found.

摘要翻译： 使用聚焦离子束进行集成电路诊断，表征或修改的方法和装置。 一种用于编辑集成电路的方法包括通过将集中的离子束施加到集成电路的外表面来获取集成电路的结构图像，以便可视化集成电路外表面下方的结构。 该方法包括使用图像来找到集成电路中的电路元件的位置，然后通过将聚焦离子束施加到所找到的位置来对电路元件执行一个或多个编辑操作。

公开(公告)号：US07488937B2

公开(公告)日：2009-02-10

申请号：US11252139

申请日：2005-10-17

申请人： Erwan Le Roy ,  William B. Thompson

发明人： Erwan Le Roy ,  William B. Thompson

IPC分类号： H01L21/00

CPC分类号： H01L21/31608 ,  G01N23/2251 ,  G01R31/307 ,  H01J37/3005 ,  H01J37/3056 ,  H01J2237/30466 ,  H01J2237/3174 ,  H01J2237/31749 ,  H01L21/02164 ,  H01L21/02214 ,  H01L21/02348 ,  H01L22/12 ,  H01L22/26 ,  H01L22/34 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

摘要： A method and system for registering a CAD layout to a Focused Ion Beam image for through-the substrate probing, without using an optical image and without requiring biasing, includes an improved method of trench endpointing during the FIB milling operation with a low beam energy. The method further includes removal of Ga at the trench floor using XeF2, as well as the deposition of an insulating layer onto the trench floor.

摘要翻译： 用于将聚焦离子束图像注册到聚焦离子束图像以用于通过基板探测而不使用光学图像并且不需要偏置的方法和系统包括在具有低光束能量的FIB铣削操作期间的沟槽终点的改进方法。 该方法还包括使用XeF2在沟槽底板处去除Ga，以及在沟槽地板上沉积绝缘层。

公开(公告)号：US20070087572A1

公开(公告)日：2007-04-19

申请号：US11527434

申请日：2006-09-26

申请人： Erwan Le Roy ,  Mark Thompson ,  William Thompson

发明人： Erwan Le Roy ,  Mark Thompson ,  William Thompson

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01J37/3056 ,  H01J37/3005

摘要： A method for observing voltage contrast from buried structures in SOI. The method includes depositing a thin transparent metal layer over the BOx to dissipate charging of the oxide, and using a low FIB beam current to avoid damage due to ion implantation and direct ion beam damage.

摘要翻译： 一种用于观察SOI中埋置结构的电压对比度的方法。 该方法包括在BOx上沉积薄的透明金属层以消散氧化物的充电，并且使用低FIB束电流以避免由于离子注入和直接离子束损伤而造成的损坏。

公开(公告)号：US07884024B2

公开(公告)日：2011-02-08

申请号：US11754466

申请日：2007-05-29

申请人： Erwan Le Roy ,  Chun-Cheng Tsao ,  Theodore R. Lundquist ,  Rajesh Kumar Jain

发明人： Erwan Le Roy ,  Chun-Cheng Tsao ,  Theodore R. Lundquist ,  Rajesh Kumar Jain

IPC分类号： H01L21/302

CPC分类号： H01L21/3065 ,  H01J37/228 ,  H01J37/3056 ,  H01J2237/2482 ,  H01J2237/30466 ,  H01J2237/31749 ,  H01L22/12 ,  H01L22/26

摘要： An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection and/or characteristics of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Resulting fringes will be a function, in part, of the thickness and/or profile of the trench floor. Milling may be controlled as a function of the detected fringe patterns.

摘要翻译： 一种使用光学干涉条纹处理集成电路的装置和方法。 在处理期间，一个或多个波长的光被引导到集成电路上，并且基于干涉条纹和其特性的检测，可以控制进一步的处理。 一种实施方案涉及集成电路的带电粒子束处理，作为干涉条纹的检测和/或特征的函数。 在集成电路的衬底中或其上执行带电粒子束沟槽铣削操作。 光线指向沟槽的地板。 干涉条纹可以由从地板反射的光与来自电路结构的光之间的建构性或破坏性干扰形成。 所产生的条纹将部分地是沟槽地板的厚度和/或轮廓的函数。 作为检测到的条纹图案的函数可以控制铣削。

公开(公告)号：US07697146B2

公开(公告)日：2010-04-13

申请号：US11362240

申请日：2006-02-24

申请人： Erwan Le Roy ,  Chun-Cheng Tsao ,  Theodore R. Lundquist

发明人： Erwan Le Roy ,  Chun-Cheng Tsao ,  Theodore R. Lundquist

IPC分类号： G01B11/02

CPC分类号： H01J37/3174 ,  B23K26/03 ,  B23K26/032 ,  B82Y10/00 ,  B82Y40/00

摘要： An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, light is directed on the integrated circuit and based upon the detection of interference fringes, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. When the floor approaches the underlying circuit structures, some light is reflected from the floor of the trench and some light penetrates the substrate and is reflected off the underlying circuit structures. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Processing may be controlled as function of the detection of interference fringes.

摘要翻译： 一种使用光学干涉条纹处理集成电路的装置和方法。 在处理期间，光被引导到集成电路上，并且基于干涉条纹的检测，可以控制进一步的处理。 一种实施方案涉及集成电路的带电粒子束处理作为干涉条纹检测的功能。 在集成电路的衬底中或其上执行带电粒子束沟槽铣削操作。 光照在沟槽的地板上。 当地板接近下面的电路结构时，一些光从沟槽的底部反射，并且一些光穿透衬底并从下面的电路结构反射。 干涉条纹可以由从地板反射的光与来自电路结构的光之间的建构性或破坏性干扰形成。 作为检测干涉条纹的功能，可以控制处理。

公开(公告)号：US06958248B1

公开(公告)日：2005-10-25

申请号：US10789336

申请日：2004-02-27

申请人： Erwan Le Roy ,  William B. Thompson

发明人： Erwan Le Roy ,  William B. Thompson

IPC分类号： G01R31/26 ,  H01J37/305 ,  H01L21/316 ,  H01L21/66

CPC分类号： H01L21/31608 ,  G01N23/2251 ,  G01R31/307 ,  H01J37/3005 ,  H01J37/3056 ,  H01J2237/30466 ,  H01J2237/3174 ,  H01J2237/31749 ,  H01L21/02164 ,  H01L21/02214 ,  H01L21/02348 ,  H01L22/12 ,  H01L22/26 ,  H01L22/34 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

摘要： A method and system for registering a CAD layout to a Focused Ion Beam image for through-the substrate probing, without using an optical image and without requiring biasing, includes an improved method of trench endpointing during the FIB milling operation with a low beam energy. The method further includes removal of Ga at the trench floor using XeF2, as well as the deposition of an insulating layer onto the trench floor.

摘要翻译： 用于将聚焦离子束图像注册到聚焦离子束图像以用于通过基板探测而不使用光学图像并且不需要偏置的方法和系统包括在具有低光束能量的FIB铣削操作期间的沟槽终点的改进方法。 该方法还包括使用XeF 2在沟槽底板处移除Ga以及在沟槽底板上沉积绝缘层。