Coplanar integration of lattice-mismatched semiconductor with silicon via wafer bonding virtual substrates
    1.
    发明授权
    Coplanar integration of lattice-mismatched semiconductor with silicon via wafer bonding virtual substrates 失效
    晶格失配的半导体与硅通过晶片键合虚拟衬底的共面整合

    公开(公告)号:US06927147B2

    公开(公告)日:2005-08-09

    申请号:US10603850

    申请日:2003-06-25

    摘要: A method of bonding lattice-mismatched semiconductors is provided. The method includes forming a Ge-based virtual substrate and depositing on the virtual substrate a CMP layer that forms a planarized virtual substrate. Also, the method includes bonding a Si substrate to the planarized virtual substrate and performing layer exfoliation on selective layers of the planarized virtual substrate producing a damaged layer of Ge. Furthermore, the method includes removing the damaged layer of Ge.

    摘要翻译: 提供了结合晶格失配的半导体的方法。 该方法包括形成Ge基虚拟衬底并在虚拟衬底上沉积形成平坦化虚拟衬底的CMP层。 此外,该方法包括将Si衬底接合到平坦化虚拟衬底并且在平坦化的虚拟衬底的选择层上进行层剥离,产生损伤的Ge层。 此外,该方法包括去除损坏的Ge层。

    High-efficiency solar-cell arrays with integrated devices and methods for forming them
    3.
    发明授权
    High-efficiency solar-cell arrays with integrated devices and methods for forming them 有权
    具有集成器件的高效率太阳能电池阵列及其形成方法

    公开(公告)号:US08604330B1

    公开(公告)日:2013-12-10

    申请号:US13310856

    申请日:2011-12-05

    IPC分类号: H01L35/34 H01L21/00

    摘要: In various embodiments, an array of discrete solar cells with associated devices such as bypass diodes is formed over a single substrate. In one instance, a method of forming a solar-cell array with integrated bypass diodes comprising: providing a semiconductor substrate, a first cell comprising a SiGe p-n junction or SiGe p-i-n junction, one or more second cells each comprising a III-V semiconductor p-n junction or III-V semiconductor p-i-n junction; forming a bypass diode that is discrete and laterally separate from its associated solar cell and comprises an unremoved portion of the first cell, the formation comprising removing an unremoved portion of the one or more second cells thereover.

    摘要翻译: 在各种实施例中,在单个衬底上形成具有诸如旁路二极管的相关器件的分立太阳能电池阵列。 在一个实例中,一种形成具有集成旁路二极管的太阳能电池阵列的方法,包括:提供半导体衬底,包含SiGe pn结或SiGe pin结的第一单元,每个包含III-V半导体pn的一个或多个第二单元 结或III-V半导体针结; 形成与其相关联的太阳能电池离散且横向分离的旁路二极管,并且包括第一电池的未移动部分,该组件包括从其中去除一个或多个第二电池的未移动部分。

    Structure and method for a high-speed semiconductor device having a Ge channel layer
    4.
    发明授权
    Structure and method for a high-speed semiconductor device having a Ge channel layer 有权
    具有Ge沟道层的高速半导体器件的结构和方法

    公开(公告)号:US08436336B2

    公开(公告)日:2013-05-07

    申请号:US11877186

    申请日:2007-10-23

    IPC分类号: H01L29/06

    摘要: The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.

    摘要翻译: 本发明提供包括应变Ge沟道层的半导体结构和设置在应变Ge沟道层上的栅极电介质。 在本发明的一个方面,提供了应变的Ge沟道MOSFET。 应变Ge沟道MOSFET包括Ge含量在50-95%之间的弛豫SiGe虚拟衬底和形成在虚拟衬底上的应变Ge沟道。 在应变Ge通道上形成栅极结构,于是形成具有在体积Si上增加的性能的MOSFET。 在本发明的另一实施例中,包括松弛的Ge沟道层和虚拟衬底的半导体结构,其中放宽的Ge沟道层设置在虚拟衬底之上。 在本发明的另一方面,提供了一种放宽的Ge沟道MOSFET。 该方法包括提供具有约100%的Ge组成的松弛虚拟衬底和形成在虚拟衬底上的松弛Ge沟道。

    MONOLITHICALLY INTEGRATED PHOTODETECTORS
    9.
    发明申请
    MONOLITHICALLY INTEGRATED PHOTODETECTORS 有权
    单一集成的光电复印机

    公开(公告)号:US20090242935A1

    公开(公告)日:2009-10-01

    申请号:US11591658

    申请日:2006-11-01

    IPC分类号: H01L31/0336 H01L31/00

    摘要: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based photodetector comprising an active region including at least a portion of the monocrystalline silicon layer. The structure also includes a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon. The structure includes at least one non-silicon photodetector comprising an active region including at least a portion of the second monocrystalline semiconductor layer.

    摘要翻译: 提供了单晶硅和单晶非硅材料和器件单片集成的方法和结构。 在一种结构中,单片集成半导体器件结构包括硅衬底和设置在硅衬底上的第一单晶半导体层,其中第一单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。 该结构还包括设置在第一区域中的第一单晶半导体层上的绝缘层和设置在第一区域中的绝缘层上的单晶硅层。 该结构包括至少一个硅基光电检测器,其包括至少部分单晶硅层的有源区。 该结构还包括第二单晶半导体层,其设置在第二区域中的第一单晶半导体层的至少一部分上且不存在于第一区域中,其中第二单晶半导体层具有与松弛硅的晶格常数不同的晶格常数 。 该结构包括至少一个非硅光电检测器,其包括包括第二单晶半导体层的至少一部分的有源区。

    Monolithically integrated light emitting devices
    10.
    发明授权
    Monolithically integrated light emitting devices 有权
    单片集成发光器件

    公开(公告)号:US07535089B2

    公开(公告)日:2009-05-19

    申请号:US11591657

    申请日:2006-11-01

    IPC分类号: H01L23/06

    摘要: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based electronic device including an element including at least a portion of the monocrystalline silicon layer. The structure also includes a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon. The structure includes at least one III-V light-emitting device including an active region including at least a portion of the second monocrystalline semiconductor layer.

    摘要翻译: 提供了单晶硅和单晶非硅材料和器件单片集成的方法和结构。 在一种结构中,单片集成半导体器件结构包括硅衬底和设置在硅衬底上的第一单晶半导体层,其中第一单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。 该结构还包括设置在第一区域中的第一单晶半导体层上的绝缘层和设置在第一区域中的绝缘层上的单晶硅层。 该结构包括至少一个硅基电子器件,其包括至少部分单晶硅层的元件。 该结构还包括第二单晶半导体层,其设置在第二区域中的第一单晶半导体层的至少一部分上且不存在于第一区域中,其中第二单晶半导体层具有与松弛硅的晶格常数不同的晶格常数 。 该结构包括至少一个III-V发光器件,其包括包括第二单晶半导体层的至少一部分的有源区。