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    Method of manufacturing fine features for thin film transistors
    1.
    发明申请
    Method of manufacturing fine features for thin film transistors 有权
    制造薄膜晶体管精细特征的方法

    公开(公告)号：US20070221611A1

    公开(公告)日：2007-09-27

    申请号：US11388731

    申请日：2006-03-24

    申请人： Eugene Chow ,  William Wong ,  Michael Chabinyc ,  Ana Arias

    发明人： Eugene Chow ,  William Wong ,  Michael Chabinyc ,  Ana Arias

    IPC分类号： H01B13/00 ,  C23F1/00

    CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L27/1292

    摘要： A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.

    摘要翻译： 一种在晶体管上制造诸如小栅电极的精细特征的工艺。 该方法涉及一种掩模的喷墨印刷和金属镀层，以在一层中制造亚像素和标准像素尺寸特征。 打印创建一个小的子像素大小的间隙掩模，用于电镀精细特征。 可以使用第二印刷掩模来保护新形成的栅极并蚀刻连接小栅极的标准像素尺寸线。

    Method using monolayer etch masks in combination with printed masks
    2.
    发明申请
    Method using monolayer etch masks in combination with printed masks 失效
    使用单层蚀刻掩模与印刷掩模组合的方法

    公开(公告)号：US20070221610A1

    公开(公告)日：2007-09-27

    申请号：US11388718

    申请日：2006-03-24

    申请人： Eugene Chow ,  William Wong ,  Michael Chabinyc ,  Jeng Lu ,  Ana Arias

    发明人： Eugene Chow ,  William Wong ,  Michael Chabinyc ,  Jeng Lu ,  Ana Arias

    IPC分类号： H01B13/00 ,  B44C1/22

    CPC分类号： H01L21/302 ,  H01L21/0271 ,  H01L21/0273 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/1292 ,  H01L29/66765

    摘要： A method to pattern films into dimensions smaller than the printed pixel mask size. A printed mask is deposited on a thin film on a substrate. The second mask layer is selectively deposited onto the film, but not to the printed mask. A third mask is then printed onto the substrate to pattern a portion of the second mask. Certain solvents are then used to remove the printed mask but not the mask layer on the thin film. The mask layer is then used to form a pattern on the thin film in combination with etching. The features formed in the thin film are smaller than the smallest dimension of the printed mask. The coated mask layer can be a self-assembled mono-layer or other material that selectively binds to the thin film.

    摘要翻译： 将薄膜图案尺寸小于印刷像素掩模尺寸的方法。 印刷的掩模沉积在基底上的薄膜上。 第二掩模层选择性地沉积在膜上，而不是印刷在掩模上。 然后将第三掩模印刷到基底上以对第二掩模的一部分进行图案化。 然后使用某些溶剂去除印刷的掩模，而不是薄膜上的掩模层。 然后将掩模层与蚀刻结合在薄膜上形成图案。 形成在薄膜中的特征小于印刷掩模的最小尺寸。 涂覆的掩模层可以是选择性地结合薄膜的自组装单层或其它材料。

    Printed transistors
    3.
    发明申请
    Printed transistors 有权
    印刷晶体管

    公开(公告)号：US20060115945A1

    公开(公告)日：2006-06-01

    申请号：US11332577

    申请日：2006-01-12

    申请人： Michael Chabinyc ,  Ana Arias

    发明人： Michael Chabinyc ,  Ana Arias

    IPC分类号： H01L21/8238

    CPC分类号： H01L51/0004 ,  B82Y10/00 ,  B82Y30/00 ,  H01L27/1285 ,  H01L27/1292 ,  H01L27/283 ,  H01L29/66742 ,  H01L51/0012 ,  H01L51/0541 ,  H01L51/0545

    摘要： A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.

    摘要翻译： 通过将改性剂涂层施加到源极和漏极触点和/或向这些触点之间的沟道区域施加晶体管。 选择改性剂涂层以调节源极/漏极/沟道区域中的表面能量图案，使得半导体印刷液体不被从通道区域拉出。 例如，可以选择用于触点的改性剂涂层以具有与用于沟道区的改性涂层基本上相同的表面能。 沉积在通道区域上的半导体印刷液体因此沉降就位（由于缺少表面能量差），并且在触点之间形成相对厚的有源半导体区域。 或者，可以选择改性剂涂层以具有比通道区域中的改性剂涂层更低的表面能，其实际上导致半导体印刷液体被拉向通道区域。

    Transistor Production Using Semiconductor Printing Fluid
    4.
    发明申请
    Transistor Production Using Semiconductor Printing Fluid 有权
    使用半导体印刷液的晶体管生产

    公开(公告)号：US20080092807A1

    公开(公告)日：2008-04-24

    申请号：US11957384

    申请日：2007-12-14

    申请人： Michael Chabinyc ,  Ana Arias

    发明人： Michael Chabinyc ,  Ana Arias

    IPC分类号： B05C11/02

    CPC分类号： H01L51/0004 ,  B82Y10/00 ,  B82Y30/00 ,  H01L27/1285 ,  H01L27/1292 ,  H01L27/283 ,  H01L29/66742 ,  H01L51/0012 ,  H01L51/0541 ,  H01L51/0545

    摘要： A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.

    摘要翻译： 通过将改性剂涂层施加到源极和漏极触点和/或向这些触点之间的沟道区域施加晶体管。 选择改性剂涂层以调节源极/漏极/沟道区域中的表面能量图案，使得半导体印刷液体不被从通道区域拉出。 例如，可以选择用于触点的改性剂涂层以具有与用于沟道区的改性涂层基本上相同的表面能。 沉积在通道区域上的半导体印刷液体因此沉降就位（由于缺少表面能量差）并且在触点之间形成相对厚的有源半导体区域。 或者，可以选择改性剂涂层以具有比通道区域中的改性剂涂层更低的表面能，其实际上导致半导体印刷液体被拉向通道区域。

    Organic thin-film transistor backplane with multi-layer contact structures and data lines
    5.
    发明申请
    Organic thin-film transistor backplane with multi-layer contact structures and data lines 有权
    具有多层接触结构和数据线的有机薄膜晶体管背板

    公开(公告)号：US20070158644A1

    公开(公告)日：2007-07-12

    申请号：US11316551

    申请日：2005-12-21

    申请人： Michael Chabinyc ,  Rene Lujan ,  Ana Arias ,  Jackson Ho

    发明人： Michael Chabinyc ,  Rene Lujan ,  Ana Arias ,  Jackson Ho

    IPC分类号： H01L29/08

    CPC分类号： H01L27/283 ,  H01L51/0037 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/105

    摘要： A backplane circuit includes an array of organic thin-film transistors (OTFTs), each OTFT including a source contact, a drain contact, and an organic semiconductor region extending between the source and drain contacts. The drain contacts in each row are connected to an address line. The source and drain contacts and the address lines are fabricated using a multi-layer structure including a relatively thick base portion formed of a relatively inexpensive metal (e.g., aluminum or copper), and a relatively thin contact layer formed of a high work function, low oxidation metal (e.g., gold) that exhibits good electrical contact to the organic semiconductor, is formed opposite at least one external surface of the base, and is located at least partially in an interface region where the organic semiconductor contacts an underlying dielectric layer.

    摘要翻译： 背板电路包括有机薄膜晶体管（OTFT）的阵列，每个OTFT包括源极接触，漏极接触以及在源极和漏极接触之间延伸的有机半导体区域。 每行的漏极触点连接到地址线。 源极和漏极触点和地址线使用包括由相对便宜的金属（例如，铝或铜）形成的相对厚的基部的多层结构以及由高功函数形成的相对较薄的接触层制造， 与有机半导体呈现良好的电接触的低氧化金属（例如，金）形成在与基底的至少一个外表面相对的位置，并且至少部分地位于有机半导体与下面的介电层接触的界面区域中。

    Method of fabrication of printed transistors
    6.
    发明申请
    Method of fabrication of printed transistors 有权
    印刷晶体管的制造方法

    公开(公告)号：US20050269570A1

    公开(公告)日：2005-12-08

    申请号：US10864570

    申请日：2004-06-08

    申请人： Michael Chabinyc ,  Ana Arias

    发明人： Michael Chabinyc ,  Ana Arias

    IPC分类号： H01L51/05 ,  H01L21/208 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/786 ,  H01L31/20 ,  H01L51/00

    CPC分类号： H01L51/0004 ,  B82Y10/00 ,  B82Y30/00 ,  H01L27/1285 ,  H01L27/1292 ,  H01L27/283 ,  H01L29/66742 ,  H01L51/0012 ,  H01L51/0541 ,  H01L51/0545

    摘要： A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.

    摘要翻译： 通过将改性剂涂层施加到源极和漏极触点和/或向这些触点之间的沟道区域施加晶体管。 选择改性剂涂层以调节源极/漏极/沟道区域中的表面能量图案，使得半导体印刷液体不被从通道区域拉出。 例如，可以选择用于触点的改性剂涂层以具有与用于沟道区的改性涂层基本上相同的表面能。 沉积在通道区域上的半导体印刷液体因此沉降就位（由于缺少表面能量差）并且在触点之间形成相对厚的有源半导体区域。 或者，可以选择改性剂涂层以具有比通道区域中的改性剂涂层更低的表面能，其实际上导致半导体印刷液体被拉向通道区域。

    Detecting defective ejector in digital lithography system
    7.
    发明申请
    Detecting defective ejector in digital lithography system 失效
    在数字光刻系统中检测有缺陷的喷射器

    公开(公告)号：US20070046705A1

    公开(公告)日：2007-03-01

    申请号：US11218416

    申请日：2005-09-01

    申请人： William Wong ,  Steven Ready ,  Ana Arias

    发明人： William Wong ,  Steven Ready ,  Ana Arias

    IPC分类号： B41J29/38

    CPC分类号： B41J29/393

    摘要： A digital lithography system prints a large-area electronic device by dividing the overall device printing process into a series of discrete feature printing sub-processes, where each feature printing sub-process involves printing both a predetermined portion (feature) of the device in a designated substrate area, and an associated test pattern in a designated test area that is remote from the feature. At the end of each feature printing sub-process, the test pattern is analyzed, e.g., using a camera and associated imaging system, to verify that the test pattern has been successfully printed. A primary ejector is used until an unsuccessfully printed test pattern is detected, at which time a secondary (reserve) ejector replaces the primary ejector and reprints the feature associated with the defective test pattern. When multiple printheads are used in parallel, analysis of the test pattern is used to efficiently identify the location of a defective ejector.

    摘要翻译： 数字光刻系统通过将整个设备打印过程划分成一系列离散特征打印子过程来打印大面积电子设备，其中每个特征打印子过程涉及将设备的预定部分（特征）打印在一个 指定的基板区域以及远离该特征的指定测试区域中的关联测试图案。 在每个特征打印子过程结束时，分析测试图案，例如使用相机和相关联的成像系统来验证测试图案是否已被成功打印。 使用初级喷射器，直到检测到未成功打印的测试图案，此时次要（预留）喷射器取代主喷射器并重印与缺陷测试图案相关的特征。 当并行使用多个打印头时，使用测试图案的分析来有效地识别有缺陷的喷射器的位置。

    Patterned structures fabricated by printing mask over lift-off pattern
    8.
    发明申请
    Patterned structures fabricated by printing mask over lift-off pattern 有权
    通过在剥离模式上印刷掩模制造的图案化结构

    公开(公告)号：US20070020883A1

    公开(公告)日：2007-01-25

    申请号：US11184304

    申请日：2005-07-18

    申请人： Ana Arias ,  Rene Lujan ,  William Wong

    发明人： Ana Arias ,  Rene Lujan ,  William Wong

    IPC分类号： H01L21/30

    CPC分类号： H01L21/027 ,  H01L21/0272 ,  H01L27/1292 ,  H01L29/66765 ,  H01L51/0016

    摘要： A patterned integrated circuit structure defining a gap or via is fabricated solely by digital printing and bulk processing. A sacrificial lift-off pattern is printed or otherwise formed over a substrate, and then covered by a blanket layer. A mask is then formed, e.g., by printing a wax pattern that covers a region of the blanket layer corresponding to the desired patterned structure, and overlaps the lift-off pattern. Exposed portions of the blanket layer are then removed, e.g., by wet etching. The printed mask and the lift-off pattern are then removed using a lift-off process that also removes any remaining portions of the blanket layer formed over the lift-off pattern. A thin-film transistor includes patterned source/drain structures that are self-aligned to an underlying gate structure by forming a photoresist lift-off pattern that is exposed and developed by a back-exposure process using the gate structure as a mask.

    摘要翻译： 限定间隙或通孔的图案化集成电路结构仅通过数字印刷和批量处理来制造。 牺牲剥离图案印刷或以其它方式形成在衬底上，然后被覆盖层覆盖。 然后形成掩模，例如通过印刷覆盖对应于所需图案化结构的橡皮布层的区域并与剥离图案重叠的蜡图案。 然后例如通过湿蚀刻除去覆盖层的暴露部分。 然后使用剥离过程去除印刷的掩模和剥离图案，剥离过程也去除在剥离图案上形成的覆盖层的任何剩余部分。 薄膜晶体管包括通过形成通过使用栅极结构作为掩模的背景曝光工艺曝光和显影的光致抗蚀剂剥离图案而与底层栅极结构自对准的图案化源极/漏极结构。

    Phase-separated composite films and methods of preparing the same
    9.
    发明申请
    Phase-separated composite films and methods of preparing the same 有权
    相分离复合膜及其制备方法

    公开(公告)号：US20060131563A1

    公开(公告)日：2006-06-22

    申请号：US11015795

    申请日：2004-12-20

    申请人： Alberto Salleo ,  Ana Arias ,  William Wong

    发明人： Alberto Salleo ,  Ana Arias ,  William Wong

    IPC分类号： H01L51/00

    CPC分类号： B82Y30/00 ,  H01L27/28 ,  H01L51/0004 ,  H01L51/0015

    摘要： Composite films formed from blends of semiconducting and insulating materials that phase separate on patterned substrates are provided. Phase separation provides isolated and encapsulated areas of semiconductor on the substrate. Processes for preparing and using such composite films are also provided, along with devices including such composite films.

    摘要翻译： 提供由在图案化衬底上相分离的半导体和绝缘材料的共混物形成的复合膜。 相分离在衬底上提供隔离和封装的半导体区域。 还提供了制备和使用这种复合膜的方法以及包括这种复合膜的装置。