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    Method for manufacturing capacitor of semiconductor memory device by two-step thermal treatment
    3.
    发明授权
    Method for manufacturing capacitor of semiconductor memory device by two-step thermal treatment 失效
    通过两步热处理制造半导体存储器件电容器的方法

    公开(公告)号：US06472319B2

    公开(公告)日：2002-10-29

    申请号：US09851910

    申请日：2001-05-09

    申请人： Seok-jun Won ,  Yun-jung Lee ,  Soon-yeon Park ,  Cha-young Yoo ,  Doo-sup Hwang ,  Eun-ae Chung ,  Wan-don Kim

    发明人： Seok-jun Won ,  Yun-jung Lee ,  Soon-yeon Park ,  Cha-young Yoo ,  Doo-sup Hwang ,  Eun-ae Chung ,  Wan-don Kim

    IPC分类号： H01L2144

    CPC分类号： H01L28/55 ,  H01L28/65

    摘要： A method for manufacturing a capacitor of a semiconductor memory device by a two-step thermal treatment is provided. A lower electrode is formed on a semiconductor substrate. A dielectric layer is formed over the lower electrode. An upper electrode formed of a noble metal is formed over the dielectric layer. The resultant having the upper electrode undergoes a first thermal treatment under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 200-600° C., which is lower than the oxidation temperature of the upper electrode. The first thermally treated resultant undergoes a second thermal treatment under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 300-900° C., which is higher than the first temperature.

    摘要翻译： 提供了通过两步热处理制造半导体存储器件的电容器的方法。 在半导体衬底上形成下电极。 在下电极上形成电介质层。 在电介质层上形成由贵金属形成的上电极。 具有上电极的所得物在包含氧的第一气氛下进行第一热处理，所述第一气氛在第一温度下被选择在低于上电极的氧化温度的200-600℃的范围内。 第一热处理产物在第二温度下在没有氧的第二气氛下进行第二热处理，第二温度选择在比第一温度高的300-900℃的范围内。

    Method for manufacturing capacitor of semiconductor memory device controlling thermal budget
    4.
    发明授权
    Method for manufacturing capacitor of semiconductor memory device controlling thermal budget 有权
    制造控制热预算的半导体存储器件电容器的方法

    公开(公告)号：US06815221B2

    公开(公告)日：2004-11-09

    申请号：US10105181

    申请日：2002-03-25

    申请人： Wan-don Kim ,  Cha-young Yoo ,  Doo-sup Hwang ,  Jae-hyun Joo ,  Eun-ae Chung ,  Yong-kuk Jeong

    发明人： Wan-don Kim ,  Cha-young Yoo ,  Doo-sup Hwang ,  Jae-hyun Joo ,  Eun-ae Chung ,  Yong-kuk Jeong

    IPC分类号： H01G706

    CPC分类号： H01L28/55 ,  H01L28/60 ,  H01L28/91

    摘要： A method for manufacturing a capacitor of a semiconductor memory device by controlling thermal budgets is provided. In the method for manufacturing a capacitor of a semiconductor memory device, a lower electrode is formed on a semiconductor substrate. The lower electrode is heat-treated with a first thermal budget. A dielectric layer is formed on the heat-treated lower electrode. The dielectric layer is crystallized by heat-treating the dielectric layer with a second thermal budget which is smaller than the first thermal budget.

    摘要翻译： 提供了一种通过控制热预算来制造半导体存储器件的电容器的方法。 在制造半导体存储器件的电容器的方法中，在半导体衬底上形成下电极。 下电极用第一热预算进行热处理。 在热处理的下电极上形成电介质层。 通过用小于第一热预算的第二热预算对介电层进行热处理来使介质层结晶。

    Methods of fabricating metal-insulator-metal capacitors with a chemical barrier layer in a lower electrode
    6.
    发明授权
    Methods of fabricating metal-insulator-metal capacitors with a chemical barrier layer in a lower electrode 有权
    在下电极中制造具有化学阻挡层的金属 - 绝缘体 - 金属电容器的方法

    公开(公告)号：US07655519B2

    公开(公告)日：2010-02-02

    申请号：US11216639

    申请日：2005-09-01

    申请人： Eun-ae Chung ,  Jae-hyoung Choi ,  Jung-hee Chung ,  Young-sun Kim ,  Cha-young Yoo

    发明人： Eun-ae Chung ,  Jae-hyoung Choi ,  Jung-hee Chung ,  Young-sun Kim ,  Cha-young Yoo

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/7687 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/75

    摘要： A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.

    摘要翻译： 金属绝缘体金属（MIM）电容器包括下电极，电介质层和上电极。 下电极包括第一导电层，第一导电层上的化学阻挡层和化学阻挡层上的第二导电层。 化学屏障层位于第一和第二导电层之间，并且是与第一和第二导电层不同的材料。 介电层位于下电极上。 上电极位于与下电极相对的电介质层上。 第一和第二导电层可以具有相同的厚度。 化学阻挡层可以比第一和第二导电层中的每一个薄。 讨论相关方法。

    METAL-INSULATOR-METAL CAPACITORS WITH A CHEMICAL BARRIER LAYER IN A LOWER ELECTRODE
    7.
    发明申请
    METAL-INSULATOR-METAL CAPACITORS WITH A CHEMICAL BARRIER LAYER IN A LOWER ELECTRODE 审中-公开
    金属绝缘体 - 金属电容器，在较低的电极中具有化学障碍层

    公开(公告)号：US20100117194A1

    公开(公告)日：2010-05-13

    申请号：US12639184

    申请日：2009-12-16

    申请人： Eun-ae Chung ,  Jae-hyoung Choi ,  Jung-hee Chung ,  Young-sun Kim ,  Cha-young Yoo

    发明人： Eun-ae Chung ,  Jae-hyoung Choi ,  Jung-hee Chung ,  Young-sun Kim ,  Cha-young Yoo

    IPC分类号： H01L29/92 ,  H01G4/06 ,  H01G4/008

    CPC分类号： H01L21/7687 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/75

    摘要： A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.

    摘要翻译： 金属绝缘体金属（MIM）电容器包括下电极，电介质层和上电极。 下电极包括第一导电层，第一导电层上的化学阻挡层和化学阻挡层上的第二导电层。 化学屏障层位于第一和第二导电层之间，并且是与第一和第二导电层不同的材料。 介电层位于下电极上。 上电极位于与下电极相对的电介质层上。 第一和第二导电层可以具有相同的厚度。 化学阻挡层可以比第一和第二导电层中的每一个薄。 讨论相关方法。

    Metal-insulator-metal capacitors with a chemical barrier layer in a lower electrode and methods of fabricating the same
    8.
    发明申请
    Metal-insulator-metal capacitors with a chemical barrier layer in a lower electrode and methods of fabricating the same 有权
    具有下电极中的化学阻挡层的金属 - 绝缘体 - 金属电容器及其制造方法

    公开(公告)号：US20060113578A1

    公开(公告)日：2006-06-01

    申请号：US11216639

    申请日：2005-09-01

    申请人： Eun-ae Chung ,  Jae-hyoung Choi ,  Jung-hee Chung ,  Young-sun Kim ,  Cha-young Yoo

    发明人： Eun-ae Chung ,  Jae-hyoung Choi ,  Jung-hee Chung ,  Young-sun Kim ,  Cha-young Yoo

    IPC分类号： H01L27/108

    CPC分类号： H01L21/7687 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/75

    摘要： A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.

    摘要翻译： 金属绝缘体金属（MIM）电容器包括下电极，电介质层和上电极。 下电极包括第一导电层，第一导电层上的化学阻挡层和化学阻挡层上的第二导电层。 化学屏障层位于第一和第二导电层之间，并且是与第一和第二导电层不同的材料。 介电层位于下电极上。 上电极位于与下电极相对的电介质层上。 第一和第二导电层可以具有相同的厚度。 化学阻挡层可以比第一和第二导电层中的每一个薄。 讨论相关方法。

    METHODS OF FORMING INTEGRATED CIRCUIT CAPACITORS HAVING COMPOSITE DIELECTRIC LAYERS THEREIN CONTAINING CRYSTALLIZATION INHIBITING REGIONS
    9.
    发明申请
    METHODS OF FORMING INTEGRATED CIRCUIT CAPACITORS HAVING COMPOSITE DIELECTRIC LAYERS THEREIN CONTAINING CRYSTALLIZATION INHIBITING REGIONS 审中-公开
    形成具有包含结晶区域的复合介电层的集成电路电容器的方法

    公开(公告)号：US20130130465A1

    公开(公告)日：2013-05-23

    申请号：US13716901

    申请日：2012-12-17

    申请人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoo Oh

    发明人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoo Oh

    IPC分类号： H01L29/92

    CPC分类号： H01L29/92 ,  H01L27/10852 ,  H01L28/40

    摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

    摘要翻译： 集成电路电容器在其中具有复合电介质层。 这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。 集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。 电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。 电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。