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14 条记录 (耗时 0.019 秒)

    Laser programmable integrated circuit
    1.
    发明授权
    Laser programmable integrated circuit 失效
    激光可编程集成电路

    公开(公告)号：US4937475A

    公开(公告)日：1990-06-26

    申请号：US246311

    申请日：1988-09-19

    申请人： F. Matthew Rhodes ,  Jack I. Raffel

    发明人： F. Matthew Rhodes ,  Jack I. Raffel

    IPC分类号： H03K19/173 ,  H03K19/177 ,  H04Q3/52

    CPC分类号： H03K19/17748 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1778 ,  H04Q3/523

    摘要： A laser programmable integrated circuit chip has a plurality of logic modules organized as rows and columns. The modules and other chip components are connected by a grid-like array of conductors. The conductors are initially unattached. Customization occurs by fusing laser diffuseable links and severing cut points on the conductors. The modules have continuous conductor lines running through them. These conductor lines aid in testing and are useful in routing and error avoidance. The chip also contains test registers to test the array of logic modules, the input/output blocks, and the conductors.

    摘要翻译： 激光可编程集成电路芯片具有被组织成行和列的多个逻辑模块。 模块和其他芯片组件通过栅格阵列的导体连接。 导体最初未连接。 通过熔合激光可漫射连接并切断导体上的切割点进行定制。 模块具有连续的导线穿过它们。 这些导线有助于测试，并且有助于路由和错误避免。 该芯片还包含用于测试逻辑模块阵列，输入/输出块和导体的测试寄存器。

    Method and apparatus for forming low resistance lateral links in a semiconductor device
    2.
    发明授权
    Method and apparatus for forming low resistance lateral links in a semiconductor device 失效
    用于在半导体器件中形成低电阻横向连杆的方法和装置

    公开(公告)号：US4636404A

    公开(公告)日：1987-01-13

    申请号：US651230

    申请日：1984-09-17

    申请人： Jack I. Raffel ,  John A. Yasaitis ,  Glenn H. Chapman

    发明人： Jack I. Raffel ,  John A. Yasaitis ,  Glenn H. Chapman

    IPC分类号： H01L23/525 ,  B05D3/06 ,  B05D5/12 ,  B23K9/00

    CPC分类号： H01L23/525 ,  H01L23/5254 ,  H01L2924/0002 ,  Y10S148/14

    摘要： A method and apparatus for reliably forming low resistance links between two aluminum conductors deposited on an insulating polysilicon or amorphous silicon layer, employ a laser to bridge a lateral gap between the conductors. The apparatus and method are ideally suited for implementing defect avoidance using redundancy in large random access memories and in complex VLSI circuits. Only a single level of metal is employed and leads to both higher density and lower capacitance in comparison to prior techniques. Resistances in the range of one to ten ohms can be achieved for gap widths of approximately two to three microns.

    摘要翻译： 一种用于可靠地形成沉积在绝缘多晶硅或非晶硅层上的两个铝导体之间的低电阻链路的方法和装置，采用激光来桥接导体之间的横向间隙。 该装置和方法理想地适用于在大型随机存取存储器和复杂VLSI电路中使用冗余来实现缺陷回避。 与现有技术相比，只采用单一级别的金属并且导致更高的密度和更低的电容。 对于大约2到3微米的间隙宽度，可实现1至10欧姆范围内的电阻。

    Voltage programmable links programmed with low current transistors
    3.
    发明授权
    Voltage programmable links programmed with low current transistors 失效
    用低电流晶体管编程的电压可编程链路

    公开(公告)号：US5390141A

    公开(公告)日：1995-02-14

    申请号：US88253

    申请日：1993-07-07

    申请人： Simon S. Cohen ,  Jack I. Raffel

    发明人： Simon S. Cohen ,  Jack I. Raffel

    IPC分类号： G11C17/18 ,  G11C13/00

    CPC分类号： G11C17/18

    摘要： An electrical path can be formed through a transformable insulator between first and second conductors by applying a voltage between such conductors across at least one selected region of the insulator. Much of the current required to complete the link is provided from parasitic capacitance of the writing circuit or from capacitance which is removable from the circuit during normal operations. As a result, small transistors of less than 100 microamps may be used in the writing circuit which applies the programming voltage.

    摘要翻译： 可以通过在绝缘体的至少一个选定区域上的这种导体之间施加电压，而在第一和第二导体之间通过可变形的绝缘体形成电路径。 完成链接所需的大部分电流由写入电路的寄生电容或在正常操作期间可从电路中移除的电容提供。 结果，在施加编程电压的写入电路中可以使用小于100微安的小晶体管。

    Capacitor memory and methods for reading, writing, and fabricating capacitor memories
    5.
    发明授权
    Capacitor memory and methods for reading, writing, and fabricating capacitor memories 失效
    电容器存储器和用于读，写和制造电容器存储器的方法

    公开(公告)号：US4242736A

    公开(公告)日：1980-12-30

    申请号：US8551

    申请日：1979-02-01

    申请人： Jack I. Raffel ,  John A. Yasaitis

    发明人： Jack I. Raffel ,  John A. Yasaitis

    IPC分类号： G11C11/22 ,  G11C11/24 ,  G11C11/4063 ,  H01L21/822 ,  H01L27/10 ,  H01L29/94 ,  G11C7/00

    CPC分类号： H01L27/101 ,  G11C11/22 ,  G11C11/24 ,  G11C11/4063 ,  H01L21/822 ,  H01L29/94 ,  H01L2924/0002

    摘要： An improved metal dual insulator semiconductor capacitor memory is disclosed. The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers. The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction. The invention also provides a method of reading stored information without disturbing adjacent cells. A small variable voltage is applied across a "flat-band" portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory. A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell. Methods to fabricate the memory are also disclosed.

    摘要翻译： 公开了一种改进的金属双绝缘体半导体电容器存储器。 存储器包含多个电容器单元，每个单元包括半导体衬底层和夹着两个绝缘体层的高电导率层。 掺杂衬底以在表面耗尽层中以与积累方向上的写入电压相当的电压提供雪崩击穿。 本发明还提供一种在不干扰相邻小区的情况下读取存储的信息的方法。 在磁滞回线的“平带”部分上施加一个小的可变电压，描述电容器存储器的电压 - 电容关系。 通过电容器的电流的改变或不存在改变电容器电池的状态。 还公开了制造存储器的方法。

    Integrated circuit packaging
    6.
    发明授权
    Integrated circuit packaging 失效
    集成电路封装

    公开(公告)号：US4027383A

    公开(公告)日：1977-06-07

    申请号：US596472

    申请日：1975-07-16

    申请人： Terry O. Herndon ,  Jack I. Raffel

    发明人： Terry O. Herndon ,  Jack I. Raffel

    IPC分类号： H01L21/48 ,  H01L23/495 ,  B01J17/00

    CPC分类号： H01L21/4821 ,  H01L23/49537 ,  H01L2924/0002 ,  Y10T29/49121

    摘要： Lead connections and packaging for integrated circuits are formed by processing elongated ribbon arrays of integrated circuit dice in groups prior to cutting the ribbon along its length to free the discrete integrated circuit products. The ribbon is adhered to the base of an elongated channel having at least one leg containing implanted lead-in conductors arranged therein as an axial series of axial arrays of conductors. The axial arrays are aligned with the circuits on the ribbons and interconnections therebetween are formed as photolithographically defined conductive coatings on a top surface of the ribbon extending from bonding pads of the integrated circuit to exposed conductor ends at a top end(s) of the leg(s). The channel ribbon assembly is cut into discrete circuits after forming such interconnections for all the circuits of the ribbon as a group. Each array of lead-in conductors is packed in high density and fans out from the channel to an array of low density lead-out conductors which may be plugged into sockets or otherwise macroscopically treated.

    摘要翻译： 用于集成电路的引线连接和封装通过在沿着其长度切割带之前处理集成电路芯片的细长带阵列而形成，以释放分立的集成电路产品。 带状物被粘附到细长通道的基部，该细长通道具有至少一个支脚，其中包含作为导向轴向排列的轴向排列的植入导入导体。 轴向阵列与带上的电路对准，并且它们之间的互连形成为在从集成电路的焊盘延伸到在腿部的顶端处的暴露导体端部的带的顶表面上的光刻定义的导电涂层 （s）。 在将带状物的所有电路作为一组形成这种互连之后，将通道带组件切割成离散电路。 每个引入导体阵列以高密度封装，并从通道中排出风扇到一组低密度导出导体，可插入插座或以其他方式进行宏观处理。

    Voltage programmable links for integrated circuits
    8.
    发明授权
    Voltage programmable links for integrated circuits 失效
    用于集成电路的电压可编程链路

    公开(公告)号：US5641703A

    公开(公告)日：1997-06-24

    申请号：US430303

    申请日：1995-04-28

    申请人： Simon S. Cohen ,  Jack I. Raffel ,  Peter W. Wyatt

    发明人： Simon S. Cohen ,  Jack I. Raffel ,  Peter W. Wyatt

    IPC分类号： H01L23/525 ,  H01L21/82

    CPC分类号： H01L23/5252 ,  H01L2924/0002

    摘要： Methods and systems are discussed for fabricating electrically programmable link structures by fabricating a first metal conductor of a refractory conductive material, composite, or an aluminum alloy which has been modified with a refractory material, then fabricating an insulating link material over the first conductor, and subsequently, depositing a second conductor over the link material. In use, an electrical path can be formed between the first and second conductors by applying a voltage between such conductors across at least one selected region of the insulator, such that the insulating link material is transformed in the region and rendered conductive to form an electrical signal path.

    摘要翻译： 讨论了用于制造电可编程链接结构的方法和系统，该方法和系统是通过制造耐火导电材料，复合材料或已经用耐火材料改性的铝合金的第一金属导体，然后在第一导体上制造绝缘连接材料，以及 随后在链路材料上沉积第二导体。 在使用中，可以通过在绝缘体的至少一个选定区域之间的这种导体之间施加电压而在第一和第二导体之间形成电路径，使得绝缘连接材料在该区域中变换并导通以形成电 信号路径。

    Dielectric isolation method using shallow oxide and polycrystalline silicon utilizing a preliminary etching step
    10.
    发明授权
    Dielectric isolation method using shallow oxide and polycrystalline silicon utilizing a preliminary etching step 失效
    使用浅层氧化物和多晶硅的介电隔离方法，利用初步蚀刻步骤

    公开(公告)号：US4231819A

    公开(公告)日：1980-11-04

    申请号：US61374

    申请日：1979-07-27

    申请人： Jack I. Raffel ,  Stephen E. Bernacki

    发明人： Jack I. Raffel ,  Stephen E. Bernacki

    IPC分类号： H01L21/02 ,  H01L21/763 ,  H01L29/06 ,  H01L21/20 ,  H01L21/302 ,  H01L21/76

    CPC分类号： H01L28/20 ,  H01L21/763 ,  H01L29/0649

    摘要： A process is described which combines polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a combination heretofore unobtainable by any other means.This isolation scheme has been used to fabricate ECL gate chains. The transistors were located in 2.5 micron thick n epi islands surrounded by 5.times.10.sup.5 ohm-cm polysilicon selectively oxidized with silicon nitride masking to a thickness of one micron. The oxide "bump" at the nitride mask was typically 3000 A and the epi-poly step height was as small as 2600 A. The circuits have polysilicon resistors and were fabricated using both thermal diffusion and ion implantation. The power-delay product of these circuits was approximately one-half that of junction isolated circuits.

    摘要翻译： 描述了结合收集器的多晶分离和碱的浅氧化物隔离的方法。 这种方法能够提供深的介电隔离，表面平面性和高密度的壁发射器几何形状，这是迄今为止通过任何其他方式无法获得的组合。 该隔离方案已被用于制造ECL门链。 晶体管位于由氮化硅选择性氧化的5×10 5欧姆 - 厘米多晶硅所围绕的2.5微米厚的外延岛中，其厚度为1微米。 氮化物掩模上的氧化物“凸块”通常为3000A，外延多层台阶高度为2600A。电路具有多晶硅电阻器，并使用热扩散和离子注入制造。 这些电路的功率延迟产物大约是结隔离电路的一半。