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1.发明授权公开(公告)号：US09774299B2
公开(公告)日：2017-09-26
申请号：US14500992
申请日：2014-09-29
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： Joseph Staudinger , Abdulrhman M. S. Ahmed , Paul R. Hart , Monte G. Miller , Nicholas J. Spence
CPC classification number: H03F1/0288 , H03F1/3247 , H03F1/3282 , H03F3/19 , H03F3/245 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H03F2201/3233 , H03F2203/21106
Abstract: An embodiment of an amplifier system includes a modifiable signal adjustment device with an RF signal adjustment circuit coupled between first and second nodes. The RF signal adjustment circuit includes an adjustable phase shifter and an adjustable attenuator coupled in series with each other. The device also includes a memory and a controller circuit. The controller circuit retrieves a phase shift value and an attenuation value from the memory. The controller circuit then controls the adjustable phase shifter to apply a phase shift corresponding to the phase shift value to an input RF signal received at the first node, and controls the adjustable attenuator to apply an attenuation corresponding to the attenuation value to the input RF signal. Applying the phase shift and the attenuation results in an output RF signal at the second node.
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公开(公告)号：US09391572B2
公开(公告)日：2016-07-12
申请号：US14300701
申请日：2014-06-10
Applicant: Freescale Semiconductor, Inc.
Inventor： Joseph Staudinger
CPC classification number: H03F3/72 , H03F1/0261 , H03F3/193 , H03F3/211 , H03F3/2171 , H03F3/2175 , H03F3/345 , H03F2200/36 , H03F2200/451 , H03F2200/537 , H03F2203/21151
Abstract: The embodiments described herein provide a radio frequency (RF) driver amplifier and method of operation. In general, the driver amplifier facilitates high performance operation in RF devices while being implemented with only n-type transistors. Using only n-type transistors in the driver amplifier can increase the operating bandwidth of the driver amplifier. Furthermore, using only n-type transistors in the driver amplifier can simplify device fabrication. The driver amplifiers and methods described herein can be used in a variety of applications. As one specific example the driver amplifier can be used in a switch-mode power amplifier (SMPA). Such a SMPA can be configured to amplify a time varying signal, such as an RF.
Abstract translation: 这里描述的实施例提供射频（RF）驱动放大器和操作方法。 通常，驱动放大器便于在仅使用n型晶体管的情况下实现RF器件的高性能操作。 在驱动放大器中仅使用n型晶体管可以增加驱动放大器的工作带宽。 此外，在驱动放大器中仅使用n型晶体管可以简化器件制造。 这里描述的驱动器放大器和方法可以用于各种应用中。 作为一个具体示例，驱动器放大器可以用在开关模式功率放大器（SMPA）中。 这样的SMPA可被配置成放大时变信号，例如RF。
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3.发明授权公开(公告)号：US09374051B2
公开(公告)日：2016-06-21
申请号：US14728196
申请日：2015-06-02
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： Abdulrhman M. S Ahmed , Mario M. Bokatius , Paul R. Hart , Joseph Staudinger , Richard E. Sweeney
CPC classification number: H03F1/0288 , G06F13/4282 , G06G7/10 , H03F3/189 , H03F3/19 , H03F3/211 , H03F3/602 , H03F3/68 , H03F2200/387 , H03F2200/438 , H03F2200/451 , H03F2203/21106 , H03F2203/21193 , H03G1/0088 , H03G2201/106 , H04L7/0079 , H04L27/22
Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.
Abstract translation: 与包括多个放大器路径的放大器一起使用的电路的实施例包括与第一电路并联的第一电路和第二电路。 第一电路包括耦合到第一功率分配器输出的第一输入，耦合到多个放大器路径的第一放大器路径的第一输出以及耦合在第一输入和第一输出之间的第一可调移相器和第一衰减器串联 。 第二电路包括耦合到第二功率分配器输出的第二输入，耦合到多个放大器路径的第二放大器路径的第二输出以及耦合在第二输入和第二输出之间的第二可调相移器。
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公开(公告)号：US09319010B1
公开(公告)日：2016-04-19
申请号：US14572396
申请日：2014-12-16
Applicant: Freescale Semiconductor, Inc.
Inventor： Joseph Staudinger , Maruf Ahmed , Hussain H. Ladhani
CPC classification number: H03F3/2171 , H03F1/0205 , H03F1/086 , H03F1/565 , H03F3/193 , H03F3/601 , H03F2200/267 , H03F2200/333 , H03F2200/387 , H03F2200/391 , H03F2200/451
Abstract: The embodiments described herein provide inverse class F (class F−1) amplifiers. In general, the inverse class F amplifiers are implemented with a transistor, an output inductance and a transmission line configured to approximate inverse class F voltage and current output waveforms by compensating the effects of the transistor's intrinsic output capacitance for some even harmonic signals while providing a low impedance for some odd harmonic signals. Specifically, the transistor is configured with the output inductance and transmission line to form a parallel LC circuit that resonates at the second harmonic frequency. The parallel LC circuit effectively creates high impedance for the second harmonic signals, thus blocking the capacitive reactance path to ground for those harmonic signals that the intrinsic output capacitance would otherwise provide. This facilitates the operation of the amplifier as an effective, high efficiency, inverse class F amplifier.
Abstract translation: 这里描述的实施例提供反向F级（F-1类）放大器。 通常，反相F放大器通过补偿晶体管的固有输出电容对某些偶次谐波信号的影响而配置为通过晶体管，输出电感和传输线来实现，从而近似反向F类电压和电流输出波形，同时提供一个 一些奇次谐波信号的低阻抗。 具体地，晶体管配置有输出电感和传输线，以形成以二次谐波频率谐振的并联LC电路。 并联LC电路有效地为二次谐波信号产生高阻抗，从而阻止本征输出电容另有提供的那些谐波信号的接地电容电抗。 这有助于放大器作为有效的，高效率的F类放大器的反相运算。
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公开(公告)号：US09628027B2
公开(公告)日：2017-04-18
申请号：US14211410
申请日：2014-03-14
Applicant: Freescale Semiconductor, Inc.
Inventor： Ramanujam Srinidhi Embar , Damon G. Holmes , Joseph Staudinger
CPC classification number: H03F1/0288 , H01L23/645 , H01L23/66 , H01L24/48 , H01L2223/6611 , H01L2224/48227 , H01L2924/19107 , H03F1/0294 , H03F3/195 , H03F3/245 , H03F3/68 , H03F2200/451 , H03F2200/537 , H03F2200/541 , Y10T29/41 , H01L2924/00014 , H01L2224/45099
Abstract: The embodiments described herein provide compensation for mutual inductance in a multi-path device. In one embodiment, a device includes a multi-path integrated device. The multi-path integrated device includes a first output and a second output. The first output is configured to be coupled to a first output lead through a first bonding wire, and the second output is configured to be coupled to a second output lead through a second bonding wire. Due to their proximity, the second bonding wire has a first mutual inductance with the first bonding wire. A first compensation network is coupled to the first output, and a second compensation network is coupled to the second output. The second compensation network is configured to have a second mutual inductance with the first compensation network. The second mutual inductance at least partially cancels the effects of the first mutual inductance.
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Patent Agency Ranking
6.发明授权Multiple-state, switch-mode power amplifier systems and methods of their operation 有权多状态，开关模式功率放大器系统及其运行方法公开(公告)号：US09515623B2
公开(公告)日：2016-12-06
申请号：US14559895
申请日：2014-12-03
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： Jean-Christophe Nanan , Jean-Jacques Bouny , Cedric Cassan , Joseph Staudinger , Hugues Beaulaton
IPC: H03F3/68 , H03F3/217 , H03F3/189 , H03F3/21 , H03F3/24 , H03F3/30 , H03F3/60 , H03F3/72 , H03M1/06 , H03M1/78
CPC classification number: H03F3/2178 , H03F3/189 , H03F3/211 , H03F3/2171 , H03F3/2175 , H03F3/2176 , H03F3/245 , H03F3/30 , H03F3/604 , H03F3/72 , H03F2200/09 , H03F2200/537 , H03F2200/541 , H03F2203/21106 , H03F2203/21142 , H03F2203/21145 , H03F2203/21157 , H03M1/0682 , H03M1/78
Abstract: An embodiment of an amplifier includes N (N>1) switch-mode power amplifier (SMPA) branches. Each SMPA branch includes two drive signal inputs and one SMPA branch output. A module coupled to the amplifier samples an input RF signal, and produces combinations of drive signals based on the samples. When an SMPA branch receives a first combination of drive signals, it produces an output signal at a first voltage level. Conversely, when the SMPA branch receives a different second combination of drive signals, it produces the output signal at a different second voltage level. Finally, when the SMPA branch receives a different third combination of drive signals, it produces the output signal at a voltage level of substantially zero. A combiner combines the output signals from all of the SMPA branches to produce a combined output signal that may have, at any given time, one of 2*N+1 quantization states.
Abstract translation: 放大器的一个实施例包括N（N> 1）个开关模式功率放大器（SMPA）分支。 每个SMPA分支包括两个驱动信号输入和一个SMPA分支输出。 耦合到放大器的模块对输入RF信号进行采样，并且基于样本产生驱动信号的组合。 当SMPA分支接收到驱动信号的第一组合时，其产生处于第一电压电平的输出信号。 相反，当SMPA分支接收到不同的驱动信号的第二组合时，它产生不同的第二电压电平的输出信号。 最后，当SMPA分支接收到不同的驱动信号的第三组合时，它产生基本为零的电压电平的输出信号。 组合器组合来自所有SMPA分支的输出信号以产生在任何给定时间可以具有2×N + 1个量化状态之一的组合输出信号。
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7.发明授权公开(公告)号：US09219453B2
公开(公告)日：2015-12-22
申请号：US14287139
申请日：2014-05-26
Applicant: Freescale Semiconductor, Inc.
Inventor： Abdulrhman M.S. Ahmed , Mario M. Bokatius , Paul R. Hart , Joseph Staudinger , Richard E. Sweeney
CPC classification number: H03F1/0288 , G06F13/4282 , G06G7/10 , H03F3/189 , H03F3/19 , H03F3/211 , H03F3/602 , H03F3/68 , H03F2200/387 , H03F2200/438 , H03F2200/451 , H03F2203/21106 , H03F2203/21193 , H03G1/0088 , H03G2201/106 , H04L7/0079 , H04L27/22
Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first series circuit and a second series circuit in parallel with the first series circuit. The first series circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first adjustable attenuator series coupled between the first input and the first output. The second series circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter and a second adjustable attenuator series coupled between the second input and the second output.
Abstract translation: 与包括多个放大器路径的放大器一起使用的电路的实施例包括与第一串联电路并联的第一串联电路和第二串联电路。 第一串联电路包括耦合到第一功率分配器输出的第一输入，耦合到多个放大器路径的第一放大器路径的第一输出，以及耦合在第一输入和第二输出之间的第一可调移相器和第一可调衰减器 第一输出。 第二串联电路包括耦合到第二功率分配器输出的第二输入，耦合到多个放大器路径的第二放大器路径的第二输出以及耦合在第二输入和第二输入之间的第二可调移相器和第二可调衰减器串联 第二输出。
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公开(公告)号：US09876475B2
公开(公告)日：2018-01-23
申请号：US15344304
申请日：2016-11-04
Applicant: Freescale Semiconductor, Inc.
Inventor： Abdulrhman M. S. Ahmed , Mario M. Bokatius , Paul R. Hart , Joseph Staudinger , Richard E. Sweeney
IPC: G06G7/12 , H03F1/02 , H03F3/21 , H03F3/60 , G06G7/10 , H03F3/68 , H03F3/189 , H04L7/00 , G06F13/42 , H03F3/19 , H04L27/22 , H03G1/00
CPC classification number: H03F1/0288 , G06F13/4282 , G06G7/10 , H03F3/189 , H03F3/19 , H03F3/211 , H03F3/602 , H03F3/68 , H03F2200/387 , H03F2200/438 , H03F2200/451 , H03F2203/21106 , H03F2203/21193 , H03G1/0088 , H03G2201/106 , H04L7/0079 , H04L27/22
Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.
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9.发明授权公开(公告)号：US09660641B2
公开(公告)日：2017-05-23
申请号：US15229312
申请日：2016-08-05
Applicant: Freescale Semiconductor, Inc.
Inventor： Bruce M. Green , Enver Krvavac , Joseph Staudinger
CPC classification number: H03K17/165 , G06F1/3206 , H03K17/162
Abstract: An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device.
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公开(公告)号：US09647611B1
公开(公告)日：2017-05-09
申请号：US14925718
申请日：2015-10-28
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： Ramanujam Srinidhi Embar , Joseph Staudinger , Margaret A. Szymanowski
CPC classification number: H03F1/0288 , H03F3/195 , H03F3/245 , H03F2200/192 , H03F2200/204 , H03F2200/411 , H03F2200/451 , H03F2200/534
Abstract: A reconfigurable Doherty power amplifier includes a packaged power splitter device, main and peaking amplifiers, and a combiner circuit. The power splitter device includes a power divider, input terminals coupled to first and second ports of the power divider, and output terminals coupled to third and fourth ports of the power divider. One of the input terminals is coupled to an RF signal input terminal, and the other input terminal is terminated. The power divider receives an input RF signal, and produces main and peaking RF signals at the third and fourth ports of the power divider, respectively. The main and peaking amplifiers amplify the main and peaking RF signals, respectively. The combiner circuit includes a summing node and a phase delay element between outputs of the main and peaking amplifiers. An RF signal output terminal is coupled to the summing node.
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