公开(公告)号：US09799760B2

公开(公告)日：2017-10-24

申请号：US14827755

申请日：2015-08-17

Applicant: Freescale Semiconductor, Inc.

Inventor： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L21/285 ,  H01L21/311 ,  H01L29/812

CPC classification number: H01L29/778 ,  H01L21/28575 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0615 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.

公开(公告)号：US09276101B2

公开(公告)日：2016-03-01

申请号：US14752066

申请日：2015-06-26

Applicant: Freescale Semiconductor, Inc.

Inventor： Bruce M. Green ,  Karen E. Moore ,  Olin Hartin

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20 ,  H01L27/06 ,  H01L49/02 ,  H01L29/47

CPC classification number: H01L29/7787 ,  H01L27/0629 ,  H01L28/60 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/475 ,  H01L29/66462

Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11-43) covered by a passivation surface layer (43) in which a T-gate electrode with sidewall extensions (48) is formed and coated with a conformal passivation layer (49) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer (43) by the conformal passivation layer (49).

Abstract translation: 提供了一种低泄漏电流开关装置（110），其包括由钝化表面层（43）覆盖的GaN-Si衬底（11-43），其中形成具有侧壁延伸部（48）的T形栅电极， 涂覆有共形钝化层（49），使得T栅极电极侧壁延伸部通过共形钝化层（49）与下面的钝化表面层（43）间隔开。

公开(公告)号：US20150357452A1

公开(公告)日：2015-12-10

申请号：US14827755

申请日：2015-08-17

Applicant: Freescale Semiconductor, Inc.

Inventor： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/778 ,  H01L21/28575 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0615 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.

Abstract translation: 半导体器件包括半导体衬底，其被配置为包括沟道，由半导体衬底支撑的第一和第二欧姆触点，与半导体衬底欧姆接触，并且彼此间隔开，以在第一和第二欧姆触点之间通过沟道 ，以及由半导体衬底支撑的第一和第二电介质层。 第一和第二欧姆触点中的至少一个延伸穿过第一和第二电介质层中的相应开口。 第二电介质层设置在第一电介质层和半导体衬底的表面之间，第二电介质层包括具有对第一介电层的干蚀刻剂的蚀刻选择性的湿蚀刻材料。

公开(公告)号：US20150311084A1

公开(公告)日：2015-10-29

申请号：US14259813

申请日：2014-04-23

Applicant: Freescale Semiconductor, Inc.

Inventor： Karen E. Moore ,  Bruce M. Green

IPC: H01L21/285 ,  H01L29/20 ,  H01L29/778 ,  H01L29/423

CPC classification number: H01L21/28587 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device is provided which includes a GaN-on-SiC substrate (50-51) and a multi-layer passivation stack (52-54) in which patterned step openings (76) are defined and filled with gate metal layers using a lift-off gate metal process to form a T-gate electrode (74) as a stepped gate electrode having sidewall extensions and a contact base portion with one or more gate ledges.

Abstract translation: 提供了一种半导体器件，其包括SiC-SiC衬底（50-51）和多层钝化堆叠（52-54），其中图案化的步骤开口（76）被限定并且使用电梯填充有栅极金属层 以形成具有侧壁延伸部的阶梯状栅电极的T形栅电极（74）和具有一个或多个栅极突起的接触基部。

公开(公告)号：US09871107B2

公开(公告)日：2018-01-16

申请号：US14719999

申请日：2015-05-22

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Bruce M. Green ,  Jenn Hwa Huang ,  Vikas S. Shilimkar

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/70 ,  H01L29/778 ,  H01L29/20 ,  H01L23/66 ,  H01L23/522 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L29/417 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L29/2003 ,  H01L21/30621 ,  H01L21/76224 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L28/10 ,  H01L29/0657 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2223/6605

Abstract: An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate. A dielectric medium may be disposed within the cavity and have a dielectric constant less than a dielectric constant of the semiconductor substrate. A method for forming the device may include forming a semiconductor substrate, forming a transistor on the semiconductor substrate, forming the first conductive feature, forming the second conductive feature, forming the conductor-less region, forming the cavity, and filling the cavity with the dielectric medium.

公开(公告)号：US09660641B2

公开(公告)日：2017-05-23

申请号：US15229312

申请日：2016-08-05

Applicant: Freescale Semiconductor, Inc.

Inventor： Bruce M. Green ,  Enver Krvavac ,  Joseph Staudinger

IPC: H03K17/16 ,  G06F1/32

CPC classification number: H03K17/165 ,  G06F1/3206 ,  H03K17/162

Abstract: An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device.

公开(公告)号：US20160308010A1

公开(公告)日：2016-10-20

申请号：US15173487

申请日：2016-06-03

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayan Viswanathan ,  Bruce M. Green ,  Darrell G. Hill ,  L. M. Mahalingam

IPC: H01L29/417 ,  H01L23/373 ,  H01L23/48 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L23/373 ,  H01L21/042 ,  H01L21/0475 ,  H01L21/28 ,  H01L21/32051 ,  H01L21/762 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/04026 ,  H01L2224/29026 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.

Abstract translation: 半导体器件的实施例包括半导体衬底，其包括主体衬底和上表面，有源区域，半导体衬底中的由凹陷表面局部限定的衬底开口，以及设置在半导体衬底上的导热层 其在有源区域内在凹入表面和半导体衬底的一部分之间延伸。 制造半导体器件的方法包括限定有源区域，在有源区域中的沟道上形成栅电极，在栅电极的相对侧上的有源区域中形成源电极和漏电极，蚀刻栅电极的衬底开口 所述半导体衬底由所述凹陷表面部分地限定，并且在所述半导体衬底上沉积导热层，所述导热层在所述沟道上在所述凹陷表面和所述半导体衬底的一部分之间延伸。

公开(公告)号：US09614046B2

公开(公告)日：2017-04-04

申请号：US15173487

申请日：2016-06-03

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayan Viswanathan ,  Bruce M. Green ,  Darrell G. Hill ,  L. M. Mahalingam

IPC: H01L31/102 ,  H01L29/417 ,  H01L23/367 ,  H01L21/762 ,  H01L21/3205 ,  H01L21/04 ,  H01L21/28 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L23/48 ,  H01L23/373

CPC classification number: H01L23/373 ,  H01L21/042 ,  H01L21/0475 ,  H01L21/28 ,  H01L21/32051 ,  H01L21/762 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/04026 ,  H01L2224/29026 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.

公开(公告)号：US09281204B2

公开(公告)日：2016-03-08

申请号：US14259813

申请日：2014-04-23

Applicant: Freescale Semiconductor, Inc.

Inventor： Karen E. Moore ,  Bruce M. Green

IPC: H01L21/461 ,  H01L21/285 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L21/28587 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device is provided which includes a GaN-on-SiC substrate (50-51) and a multi-layer passivation stack (52-54) in which patterned step openings (76) are defined and filled with gate metal layers using a lift-off gate metal process to form a T-gate electrode (74) as a stepped gate electrode having sidewall extensions and a contact base portion with one or more gate ledges.

Abstract translation: 提供了一种半导体器件，其包括SiC-SiC衬底（50-51）和多层钝化堆叠（52-54），其中图案化的步骤开口（76）被限定并且使用电梯填充有栅极金属层 以形成具有侧壁延伸部的阶梯状栅电极的T形栅电极（74）和具有一个或多个栅极突起的接触基部。

公开(公告)号：US20150295075A1

公开(公告)日：2015-10-15

申请号：US14752066

申请日：2015-06-26

Applicant: Freescale Semiconductor, Inc.

Inventor： Bruce M. Green ,  Karen E. Moore ,  Olin Hartin

IPC: H01L29/778 ,  H01L29/47 ,  H01L27/06 ,  H01L49/02 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L27/0629 ,  H01L28/60 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/475 ,  H01L29/66462

Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11-43) covered by a passivation surface layer (43) in which a T-gate electrode with sidewall extensions (48) is formed and coated with a conformal passivation layer (49) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer (43) by the conformal passivation layer (49).

Abstract translation: 提供了一种低泄漏电流开关装置（110），其包括由钝化表面层（43）覆盖的GaN-Si衬底（11-43），其中形成具有侧壁延伸部（48）的T形栅电极， 涂覆有共形钝化层（49），使得T栅极电极侧壁延伸部通过共形钝化层（49）与下面的钝化表面层（43）间隔开。