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    ETCH BIAS HOMOGENIZATION
    1.
    发明申请
    ETCH BIAS HOMOGENIZATION 有权
    ETCH BIAS均质化

    公开(公告)号：US20130292633A1

    公开(公告)日：2013-11-07

    申请号：US13463245

    申请日：2012-05-03

    申请人： Fabio Pellizzer ,  Hernan A. Castro ,  Eddie T. Flores

    发明人： Fabio Pellizzer ,  Hernan A. Castro ,  Eddie T. Flores

    IPC分类号： H01L45/00 ,  H01L21/82 ,  H01L21/8239

    CPC分类号： H01L45/1273 ,  H01L21/32134 ,  H01L21/76838 ,  H01L27/101 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

    摘要： Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned.

    摘要翻译： 提供了使用蚀刻偏压均化形成的方法和存储器件。 使用蚀刻偏压均化形成存储器件的一个示例性方法包括在衬底上形成相应电平的导电材料。 在对相应级别的导电材料进行图案化期间，每个相应级别的导电材料电耦合到衬底上的对应电路，使得每个相应级别的导电材料在其图案化期间具有均质化的蚀刻偏压。 电耦合到衬底上的对应电路的每个相应级别的导电材料被图案化。

    Etch bias homogenization
    2.
    发明授权
    Etch bias homogenization 有权
    蚀刻偏差匀浆

    公开(公告)号：US08785314B2

    公开(公告)日：2014-07-22

    申请号：US13463245

    申请日：2012-05-03

    申请人： Fabio Pellizzer ,  Hernan A. Castro ,  Eddie T. Flores

    发明人： Fabio Pellizzer ,  Hernan A. Castro ,  Eddie T. Flores

    IPC分类号： H01L21/44 ,  H01L21/3213 ,  H01L21/768

    CPC分类号： H01L45/1273 ,  H01L21/32134 ,  H01L21/76838 ,  H01L27/101 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

    摘要： Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned.

    摘要翻译： 提供了使用蚀刻偏压均化形成的方法和存储器件。 使用蚀刻偏压均化形成存储器件的一个示例性方法包括在衬底上形成相应电平的导电材料。 在对相应级别的导电材料进行图案化期间，每个相应级别的导电材料电耦合到衬底上的对应电路，使得每个相应级别的导电材料在其图案化期间具有均质化的蚀刻偏压。 电耦合到衬底上的对应电路的每个相应级别的导电材料被图案化。

    Forming phase change memory cells
    6.
    发明授权
    Forming phase change memory cells 有权
    形成相变存储单元

    公开(公告)号：US08536013B2

    公开(公告)日：2013-09-17

    申请号：US13114966

    申请日：2011-05-24

    申请人： Yudong Kim ,  Fabio Pellizzer

    发明人： Yudong Kim ,  Fabio Pellizzer

    IPC分类号： H01L21/62

    CPC分类号： H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： Small phase change memory cells may be formed by forming a segmented heater over a substrate. A stop layer may be formed over the heater layer and segmented with the heater layer. Then, sidewall spacers may be formed over the segmented heater to define an aperture between the sidewall spacers that may act as a mask for etching the stop layer over the segmented heater. As a result of the etching using the sidewall spacers as a mask, sublithographic pore may be formed over the heater. Phase change material may be formed within the pore.

    摘要翻译： 可以通过在衬底上形成分段加热器来形成小相变存储器单元。 停止层可以形成在加热器层上并且与加热器层分段。 然后，侧壁间隔物可以形成在分段加热器上方，以在侧壁间隔物之间​​形成孔，其可用作蚀刻分段加热器上的停止层的掩模。 作为使用侧壁间隔物作为掩模的蚀刻的结果，可以在加热器上形成亚光刻孔。 相变材料可以在孔内形成。

    MEMORY CELLS AND MEMORY CELL FORMATION METHODS USING SEALING MATERIAL
    7.
    发明申请
    MEMORY CELLS AND MEMORY CELL FORMATION METHODS USING SEALING MATERIAL 有权

    公开(公告)号：US20130207068A1

    公开(公告)日：2013-08-15

    申请号：US13369654

    申请日：2012-02-09

    申请人： Fabio Pellizzer

    发明人： Fabio Pellizzer

    IPC分类号： H01L27/24 ,  H01L21/62

    CPC分类号： H01L45/16 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1675

    摘要： Memory cells, arrays of memory cells, and methods of forming the same with sealing material on sidewalls thereof are disclosed herein. One example of forming a memory cell includes forming a stack of materials, forming a trench to a first depth in the stack of materials such that a portion of at least one of the active storage element material and the active select device material is exposed on sidewalls of the trench. A sealing material is formed on the exposed portion of the at least one of the active storage element material and the active select device material and the trench is deepened such that a portion of the other of the at least one of the active storage element material and the active select device material is exposed on the sidewalls of the trench.

    Phase change memory with ovonic threshold switch
    8.
    发明授权
    Phase change memory with ovonic threshold switch 有权
    相位变化记忆体带有超声门限开关

    公开(公告)号：US08084789B2

    公开(公告)日：2011-12-27

    申请号：US12700440

    申请日：2010-02-04

    申请人： Fabio Pellizzer ,  Agostino Pirovano

    发明人： Fabio Pellizzer ,  Agostino Pirovano

    IPC分类号： H01L29/76

    CPC分类号： H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1675

    摘要： A phase change memory includes a memory element and a selection element. The memory element is embedded in a dielectric and includes a resistive element having at least one sublithographic dimension and a storage region in contact with the resistive element. The selection element includes a chalcogenic material embedded in a dielectric. The chalcogenic material and the storage region are part of a stack having a common etched edge.

    摘要翻译： 相变存储器包括存储元件和选择元件。 存储元件嵌入在电介质中，并且包括具有至少一个亚光刻尺寸的电阻元件和与电阻元件接触的存储区域。 选择元件包括埋在电介质中的硫属材料。 硫属材料和存储区域是具有共同蚀刻边缘的堆叠的一部分。

    Self-Aligned Bipolar Junction Transistors
    10.
    发明申请
    Self-Aligned Bipolar Junction Transistors 审中-公开
    自对准双极结晶体管

    公开(公告)号：US20110084247A1

    公开(公告)日：2011-04-14

    申请号：US12969652

    申请日：2010-12-16

    申请人： Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

    发明人： Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

    IPC分类号： H01L45/00 ,  H01L27/082

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/24 ,  H01L29/66272

    摘要： A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.

    摘要翻译： 通过形成公共导电区域，在公共导电区域上的自身有效区域中延伸的多个控制区域，多个硅化物保护带和至少一个控制接触区域来形成多个双极晶体管。 在第二导电区域和控制接触区域上形成硅化物区域。 可以通过在所选择的硅化物保护条的第一侧选择性地注入第一导电类型的掺杂剂区域来形成第二导电区域。 通过在所选择的硅化物保护带的第二侧选择性地注入相反的导电型掺杂剂来形成控制接触区域。