Drift mitigation for multi-bits phase change memory
    2.
    发明授权
    Drift mitigation for multi-bits phase change memory 有权
    用于多位相变存储器的漂移减轻

    公开(公告)号:US09269435B2

    公开(公告)日:2016-02-23

    申请号:US14507144

    申请日:2014-10-06

    Abstract: An RC-based sensing method and computer program product to effectively sense the cell resistance of a programmed Phase Change Material (PCM) memory cell. The sensing method ensures the same physical configuration of each cell (after programming): same amorphous volume, same trap density/distribution, etc. The sensing method is based on a metric: the RC based sense amplifier implements two trigger points. The measured time interval between these two points is used as the metric to determine whether the programmed cell state, e.g., resistance, is programmed into desired value. The RC-based sensing method is embedded into an iterative PCM cell programming technique to ensure a tight distribution of resistance at each level after programming; and ensure the probability of level aliasing is very small, leading to less problematic drift.

    Abstract translation: 一种基于RC的感测方法和计算机程序产品,用于有效地检测编程的相变材料(PCM)存储单元的单元电阻。 感测方法确保每个单元的相同物理配置(编程后):相同的无定形体积,相同的阱密度/分布等。感测方法基于度量:基于RC的感测放大器实现两个触发点。 将这两个点之间的测量时间间隔用作度量以确定编程的单元状态(例如电阻)是否被编程为期望值。 基于RC的感测方法被嵌入到迭代PCM单元编程技术中,以确保编程后各层电阻的紧密分配; 并确保层次混叠的概率非常小,导致较少的有问题的漂移。

    Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor
    3.
    发明授权
    Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor 有权
    自对准工艺制造具有周围栅极存取晶体管的存储单元阵列

    公开(公告)号:US09240324B2

    公开(公告)日:2016-01-19

    申请号:US14328921

    申请日:2014-07-11

    Abstract: A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, etching a gate contact region for the word line between the pair of pillars, forming a spacer of electrically insulating material in the gate contact region, and depositing a gate contact between the pair of pillars to be in electrical contact with the gate material such that the spacer surrounds the gate contact.

    Abstract translation: 一种防止栅极接触与衬底上的多个存储器单元的源极接触电连接的方法。 该方法包括沉积和蚀刻栅极材料以部分地填充柱之间的空间并形成用于存储单元的字线,蚀刻一对柱之间的字线的栅极接触区域,形成电绝缘材料的间隔物 所述栅极接触区域以及在所述一对柱之间沉积栅极接触以与所述栅极材料电接触,使得所述间隔物围绕所述栅极接触。

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