公开(公告)号：US20180158931A1

公开(公告)日：2018-06-07

申请号：US15876606

申请日：2018-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Cheng CHI ,  Fee Li LIE ,  Chi-Chun LIU ,  Ruilong XIE

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/22 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US20170352654A1

公开(公告)日：2017-12-07

申请号：US15170109

申请日：2016-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Cheng CHI

IPC: H01L27/088 ,  H01L29/45 ,  H01L29/08 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/285 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/0217 ,  H01L21/02636 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/66795

Abstract: A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.

公开(公告)号：US20180374935A1

公开(公告)日：2018-12-27

申请号：US16056934

申请日：2018-08-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Cheng CHI ,  Fee Li LIE ,  Chi-Chun LIU ,  Ruilong XIE

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/033 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/51 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/22 ,  H01L29/49

CPC classification number: H01L29/66795 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/22 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US20180090374A1

公开(公告)日：2018-03-29

申请号：US15817554

申请日：2017-11-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Cheng CHI ,  Ruilong XIE

IPC: H01L21/768 ,  H01L29/45 ,  H01L29/417 ,  H01L29/06 ,  H01L27/088 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/45

Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.

公开(公告)号：US20180006028A1

公开(公告)日：2018-01-04

申请号：US15708911

申请日：2017-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Cheng CHI

IPC: H01L27/088 ,  H01L29/45 ,  H01L29/08 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/285 ,  H01L29/66 ,  H01L21/8234

Abstract: A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.