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    Bi-layer gate cap for self-aligned contact formation
    1.
    发明授权
    Bi-layer gate cap for self-aligned contact formation 有权
    用于自对准接触形成的双层栅极盖

    公开(公告)号：US09064801B1

    公开(公告)日：2015-06-23

    申请号：US14161721

    申请日：2014-01-23

    申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  Samsung Electronics Co., Ltd.

    发明人： David V. Horak ,  Jin Wook Lee ,  Daniel Pham ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan

    IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L29/51 ,  H01L21/283

    CPC分类号： H01L21/283 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

    摘要： A method of forming a semiconductor structure includes forming a metal gate above a semiconductor substrate and gate spacers adjacent to the metal gate surrounded by an interlevel dielectric (ILD) layer. The gate spacers and the metal gate are recessed until a height of the metal gate is less than a height of the gate spacers. An etch stop liner is deposited above the gate spacers and the metal gate. A gate cap is deposited above the etch stop liner to form a bi-layer gate cap. A contact hole is formed in the ILD layer adjacent to the metal gate, the etch stop liner in the bi-layer gate cap prevents damage of the gate spacers during formation of the contact hole. A conductive material is deposited in the contact hole to form a contact to a source-drain region in the semiconductor substrate.

    摘要翻译： 形成半导体结构的方法包括在半导体衬底之上形成金属栅极和邻近由层间电介质（ILD）层围绕的金属栅极的栅极间隔。 栅极间隔物和金属栅极凹入直到金属栅极的高度小于栅极间隔物的高度。 蚀刻停止衬垫沉积在栅极间隔物和金属栅极上方。 栅极盖沉积在蚀刻停止衬垫上方以形成双层栅极盖。 在与金属栅极相邻的ILD层中形成接触孔，双层栅极帽中的蚀刻停止衬垫防止在形成接触孔期间损坏栅极间隔物。 导电材料沉积在接触孔中以与半导体衬底中的源极 - 漏极区形成接触。

    Integrated circuits having gate cap protection and methods of forming the same
    3.
    发明授权
    Integrated circuits having gate cap protection and methods of forming the same 有权
    具有栅极盖保护的集成电路及其形成方法

    公开(公告)号：US09269611B2

    公开(公告)日：2016-02-23

    申请号：US14159944

    申请日：2014-01-21

    申请人： GLOBALFOUNDRIES, Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Daniel Thanh Khae Pham ,  Xiuyu Cai ,  Bala Subramanian Pranatharthi Haran ,  Charan Veera Venkata Satya Surisetty ,  Jin Wook Lee ,  Shom Ponoth ,  David V. Horak

    IPC分类号： H01L29/78 ,  H01L21/768

    CPC分类号： H01L21/76816 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.

    摘要翻译： 提供了形成集成电路的集成电路和方法。 集成电路包括覆盖基底的栅电极结构。 栅极电极结构包括栅电极，栅极设置在栅电极上，侧壁间隔件邻近栅电极结构的侧壁设置。 源极和漏极区域形成在与栅电极结构对准的基底衬底中。 第一电介质层设置成与侧壁间隔物相邻。 侧壁间隔件和盖在第一电介质层的顶表面下方具有凹陷表面，并且保护层设置在凹入表面之上。 第二电介质层设置在第一电介质层和保护层之上。 电互连通过第一介电层和第二介电层设置，并且电互连与相应的源区和漏区电连通。

    CONTACT FORMATION FOR ULTRA-SCALED DEVICES
    9.
    发明申请
    CONTACT FORMATION FOR ULTRA-SCALED DEVICES 有权
    超声波设备的接触形式

    公开(公告)号：US20140339629A1

    公开(公告)日：2014-11-20

    申请号：US13894513

    申请日：2013-05-15

    申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    发明人： Ruilong Xie ,  Shom Ponoth ,  David V. Horak ,  Balasubramanian Pranatharthiharan

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7827 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66666

    摘要： Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling.

    摘要翻译： 本发明的实施例提供了用于形成栅极和源极/漏极（S / D）触点的方法。 具体地，半导体器件包括形成在衬底上的栅极晶体管，形成在沟槽硅化物（TS）层上并且邻近栅极晶体管定位的S / D接触，以及形成在栅极晶体管上的栅极接触，其中至少一个 栅极触点的一部分在TS层上对齐。 这种结构使得能够与TS层接触，从而减小栅极接触和源极/漏极之间的距离，这对于超区域缩放是期望的。