公开(公告)号：US09530770B2

公开(公告)日：2016-12-27

申请号：US14261021

申请日：2014-04-24

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Alexandru Romanescu ,  Gerd Zschätzsch ,  Christian Schippel

IPC: H01L21/20 ,  H01L27/06 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L28/24 ,  H01L29/665 ,  H01L29/78

Abstract: Integrated circuits having resistor structures formed from gate metal and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a transistor area. The method deposits a gate metal over the resistor area and the transistor area of the semiconductor substrate, and the gate metal forms a gate metal layer in the resistor area. The method includes etching the gate metal to form a resistor structure from the gate metal layer in the resistor area. Further, the method includes forming contacts to the resistor structure in the resistor area.

Abstract translation: 提供了具有由栅极金属形成的电阻结构的集成电路及其制造方法。 在一个实施例中，制造集成电路的方法包括：提供具有电阻区域和晶体管区域的半导体衬底。 该方法在电阻器区域和半导体衬底的晶体管区域上沉积栅极金属，并且栅极金属在电阻器区域中形成栅极金属层。 该方法包括蚀刻栅极金属以从电阻器区域中的栅极金属层形成电阻器结构。 此外，该方法包括在电阻器区域中形成与电阻器结构的接触。

公开(公告)号：US09324831B2

公开(公告)日：2016-04-26

申请号：US14461713

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerd Zschätzsch ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/66545 ,  H01L21/02381 ,  H01L21/02532 ,  H01L29/66575 ,  H01L29/66651

Abstract: Methods for forming gates without spacers and the resulting devices are disclosed. Embodiments may include forming a channel layer on a substrate; forming a dummy gate on the channel layer; forming an interlayer dielectric (ILD) on the channel layer and surrounding the dummy gate; forming a trench within the ILD and the channel layer by removing the dummy gate and the channel layer below the dummy gate; forming an un-doped channel region at the bottom of the trench; and forming a gate above the un-doped channel region within the trench.

Abstract translation: 公开了用于形成没有间隔物的栅极和所得到的器件的方法。 实施例可以包括在衬底上形成沟道层; 在通道层上形成一个虚拟栅极; 在沟道层上形成层间电介质（ILD）并围绕虚拟栅极; 通过去除虚拟栅极以下的虚拟栅极和沟道层，在ILD和沟道层内形成沟槽; 在沟槽的底部形成未掺杂沟道区; 以及在沟槽内的未掺杂沟道区上方形成栅极。

公开(公告)号：US20160071886A1

公开(公告)日：2016-03-10

申请号：US14934369

申请日：2015-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerd Zschätzsch ,  Stefan Flachowsky ,  Dominic Thurmer

IPC: H01L27/12 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/2254 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66803 ,  H01L29/7834 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor material positioned above a substrate and a gate structure positioned above a surface of the semiconductor material, the gate structure covering a non-planar surface portion of the surface. A sidewall spacer is positioned adjacent to the gate structure and includes first dopants having one of an N-type and a P-type conductivity, wherein the sidewall spacer covers an entire sidewall surface of the gate structure and partially covers the surface of the semiconductor material. Source/drain extension regions that include the first dopants are positioned within the non-planar surface portion and in alignment with the sidewall spacer, wherein a concentration of the first dopants within a portion of the sidewall spacer proximate the non-planar surface portion substantially corresponds to a concentration of the first dopants within the source/drain extension regions proximate the non-planar surface portion.

Abstract translation: 半导体器件包括位于衬底上方的半导体材料和位于半导体材料表面之上的栅极结构，该栅极结构覆盖该表面的非平面表面部分。 侧壁间隔物定位成与栅极结构相邻，并且包括具有N型和P型导电体之一的第一掺杂剂，其中侧壁间隔物覆盖栅极结构的整个侧壁表面并且部分覆盖半导体材料的表面 。 包括第一掺杂剂的源极/漏极延伸区域位于非平面表面部分内并且与侧壁间隔物对准，其中邻近非平坦表面部分的侧壁间隔部分内的第一掺杂剂的浓度基本对应于 到靠近非平面表面部分的源极/漏极延伸区域内的第一掺杂剂的浓度。

公开(公告)号：US20160064382A1

公开(公告)日：2016-03-03

申请号：US14475720

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky ,  Gerd Zschätzsch

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28097 ,  H01L21/3083 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4941 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

Abstract: The present disclosure provides a method of forming a semiconductor device structure with selectively fabricating semiconductor device structures having fully silicided (FuSi) gates and partially silicided gates. In aspects of the present disclosure, a semiconductor device structure with a first semiconductor device and a second semiconductor device is provided, wherein each of the first and second semiconductor devices includes a gate structure over an active region, each of the gate structures having a gate electrode material and a gate dielectric material. The gate electrode material of the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed during the silicidation process.

Abstract translation: 本公开提供了一种形成半导体器件结构的方法，其选择性地制造具有完全硅化（FuSi）栅极和部分硅化栅极的半导体器件结构。 在本公开的方面中，提供了具有第一半导体器件和第二半导体器件的半导体器件结构，其中第一和第二半导体器件中的每一个在有源区域上包括栅极结构，每个栅极结构具有栅极 电极材料和栅极电介质材料。 第一半导体器件的栅电极材料凹陷，导致凹陷的第一栅电极材料，其在随后的硅化工艺期间被完全硅化。 在第二半导体器件的栅极电极材料上，在硅化处理期间形成硅化物部分。

公开(公告)号：US20160204217A1

公开(公告)日：2016-07-14

申请号：US15076895

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky ,  Gerd Zschätzsch

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/161 ,  H01L29/78 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28097 ,  H01L21/3083 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4941 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor product with certain devices having a first device with a fully silicided (FuSi) gate and a second device with a partially silicided gate is disclosed. In one example, the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed above a layer of polysilicon or amorphous silicon during the silicidation process.

Abstract translation: 具有某些器件的半导体产品具有具有完全硅化（FuSi）栅极的第一器件和具有部分硅化栅极的第二器件。 在一个示例中，第一半导体器件凹入，导致凹陷的第一栅电极材料，其在随后的硅化工艺期间被完全硅化。 在第二半导体器件的栅电极材料上，在硅化处理期间，在多晶硅层或非晶硅层之上形成硅化物部分。

公开(公告)号：US20150311272A1

公开(公告)日：2015-10-29

申请号：US14261021

申请日：2014-04-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alexandru Romanescu ,  Gerd Zschätzsch ,  Christian Schippel

IPC: H01L49/02 ,  H01L27/06 ,  H01L21/28

CPC classification number: H01L27/0629 ,  H01L28/24 ,  H01L29/665 ,  H01L29/78

Abstract: Integrated circuits having resistor structures formed from gate metal and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a transistor area. The method deposits a gate metal over the resistor area and the transistor area of the semiconductor substrate, and the gate metal forms a gate metal layer in the resistor area. The method includes etching the gate metal to form a resistor structure from the gate metal layer in the resistor area. Further, the method includes forming contacts to the resistor structure in the resistor area.

Abstract translation: 提供了具有由栅极金属形成的电阻结构的集成电路及其制造方法。 在一个实施例中，制造集成电路的方法包括：提供具有电阻区域和晶体管区域的半导体衬底。 该方法在电阻器区域和半导体衬底的晶体管区域上沉积栅极金属，并且栅极金属在电阻器区域中形成栅极金属层。 该方法包括蚀刻栅极金属以从电阻器区域中的栅极金属层形成电阻器结构。 此外，该方法包括在电阻器区域中形成与电阻器结构的接触。

公开(公告)号：US09368513B2

公开(公告)日：2016-06-14

申请号：US14934369

申请日：2015-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerd Zschätzsch ,  Stefan Flachowsky ,  Dominic Thurmer

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L27/1211 ,  H01L21/2254 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66803 ,  H01L29/7834 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor material positioned above a substrate and a gate structure positioned above a surface of the semiconductor material, the gate structure covering a non-planar surface portion of the surface. A sidewall spacer is positioned adjacent to the gate structure and includes first dopants having one of an N-type and a P-type conductivity, wherein the sidewall spacer covers an entire sidewall surface of the gate structure and partially covers the surface of the semiconductor material. Source/drain extension regions that include the first dopants are positioned within the non-planar surface portion and in alignment with the sidewall spacer, wherein a concentration of the first dopants within a portion of the sidewall spacer proximate the non-planar surface portion substantially corresponds to a concentration of the first dopants within the source/drain extension regions proximate the non-planar surface portion.

Abstract translation: 半导体器件包括位于衬底上方的半导体材料和位于半导体材料表面之上的栅极结构，该栅极结构覆盖该表面的非平面表面部分。 侧壁间隔物定位成与栅极结构相邻，并且包括具有N型和P型导电体之一的第一掺杂剂，其中侧壁间隔物覆盖栅极结构的整个侧壁表面并且部分覆盖半导体材料的表面 。 包括第一掺杂剂的源极/漏极延伸区域位于非平面表面部分内并且与侧壁间隔物对准，其中邻近非平坦表面部分的侧壁间隔部分内的第一掺杂剂的浓度基本对应于 到靠近非平面表面部分的源极/漏极延伸区域内的第一掺杂剂的浓度。

公开(公告)号：US09349734B2

公开(公告)日：2016-05-24

申请号：US14475720

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky ,  Gerd Zschätzsch

IPC: H01L21/336 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L27/06

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28097 ,  H01L21/3083 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4941 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

Abstract: The present disclosure provides a method of forming a semiconductor device structure with selectively fabricating semiconductor device structures having fully silicided (FuSi) gates and partially silicided gates. In aspects of the present disclosure, a semiconductor device structure with a first semiconductor device and a second semiconductor device is provided, wherein each of the first and second semiconductor devices includes a gate structure over an active region, each of the gate structures having a gate electrode material and a gate dielectric material. The gate electrode material of the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed during the silicidation process.

Abstract translation: 本公开提供了一种形成半导体器件结构的方法，其选择性地制造具有完全硅化（FuSi）栅极和部分硅化栅极的半导体器件结构。 在本公开的方面中，提供了具有第一半导体器件和第二半导体器件的半导体器件结构，其中第一和第二半导体器件中的每一个在有源区域上包括栅极结构，每个栅极结构具有栅极 电极材料和栅极电介质材料。 第一半导体器件的栅电极材料凹陷，导致凹陷的第一栅电极材料，其在随后的硅化工艺期间被完全硅化。 在第二半导体器件的栅极电极材料上，在硅化处理期间形成硅化物部分。

公开(公告)号：US20150372100A1

公开(公告)日：2015-12-24

申请号：US14309586

申请日：2014-06-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gerd Zschätzsch ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits having improved contacts and improved methods for fabricating integrated circuits having contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a source/drain region. The method deposits an interlayer dielectric material over the semiconductor substrate. Further, the method etches the interlayer dielectric material to form a hole defining an exposed portion of the source/drain region. The method includes forming a contact forming a contact in the hole over the exposed portion of the source/drain region and forming an interconnect in the hole over the contact.

Abstract translation: 提供具有改进的接触的集成电路和用于制造具有触点的集成电路的改进方法。 在一个实施例中，一种用于制造集成电路的方法包括：提供具有源极/漏极区域的半导体衬底。 该方法在半导体衬底上沉积层间电介质材料。 此外，该方法蚀刻层间电介质材料以形成限定源极/漏极区域的暴露部分的孔。 该方法包括在源极/漏极区域的暴露部分上形成在孔中形成接触的接触，并且在接触件上方的孔中形成互连。